^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_ALPHA_FUTEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_ALPHA_FUTEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/futex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) __ASM_SMP_MB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "1: ldl_l %0,0(%2)\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) insn \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "2: stl_c %1,0(%2)\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) " beq %1,4f\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) " mov $31,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "3: .subsection 2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "4: br 1b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) " .previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) EXC(1b,3b,$31,%1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXC(2b,3b,$31,%1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) : "=&r" (oldval), "=&r"(ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) : "r" (uaddr), "r"(oparg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 __user *uaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int oldval = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (!access_ok(uaddr, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) case FUTEX_OP_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __futex_atomic_op("mov %3,%1\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case FUTEX_OP_ADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __futex_atomic_op("addl %0,%3,%1\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case FUTEX_OP_OR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __futex_atomic_op("or %0,%3,%1\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case FUTEX_OP_ANDN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __futex_atomic_op("andnot %0,%3,%1\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case FUTEX_OP_XOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __futex_atomic_op("xor %0,%3,%1\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *oval = oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 oldval, u32 newval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int ret = 0, cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!access_ok(uaddr, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __ASM_SMP_MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "1: ldl_l %1,0(%3)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) " cmpeq %1,%4,%2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) " beq %2,3f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) " mov %5,%2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "2: stl_c %2,0(%3)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) " beq %2,4f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "3: .subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "4: br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) " .previous\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) EXC(1b,3b,$31,%0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EXC(2b,3b,$31,%0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) : "+r"(ret), "=&r"(prev), "=&r"(cmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) : "r"(uaddr), "r"((long)(int)oldval), "r"(newval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *uval = prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* _ASM_ALPHA_FUTEX_H */