Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __ASM_ALPHA_FPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __ASM_ALPHA_FPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <asm/special_insns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <uapi/asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /* The following two functions don't need trapb/excb instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    around the mf_fpcr/mt_fpcr instructions because (a) the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    never generates arithmetic faults and (b) call_pal instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)    are implied trap barriers.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) rdfpcr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	unsigned long tmp, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		"ftoit $f0,%0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		"mf_fpcr $f0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		"ftoit $f0,%1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		"itoft %0,$f0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		: "=r"(tmp), "=r"(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		"stt $f0,%0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		"mf_fpcr $f0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		"stt $f0,%1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		"ldt $f0,%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		: "=m"(tmp), "=m"(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) wrfpcr(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		"ftoit $f0,%0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		"itoft %1,$f0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		"mt_fpcr $f0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		"itoft %0,$f0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		: "=&r"(tmp) : "r"(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		"stt $f0,%0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		"ldt $f0,%1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		"mt_fpcr $f0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		"ldt $f0,%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		: "=m"(tmp) : "m"(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) swcr_update_status(unsigned long swcr, unsigned long fpcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	/* EV6 implements most of the bits in hardware.  Collect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	   the acrued exception bits from the real fpcr.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	if (implver() == IMPLVER_EV6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		swcr &= ~IEEE_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return swcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern unsigned long alpha_read_fp_reg (unsigned long reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif /* __ASM_ALPHA_FPU_H */