Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_EXTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_EXTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * About the exception table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * - insn is a 32-bit pc-relative offset from the faulting insn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * - nextinsn is a 16-bit offset off of the faulting instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *   (not off of the *next* instruction as branches are).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * - errreg is the register in which to place -EFAULT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * - valreg is the final target register for the load sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *   and will be zeroed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Either errreg or valreg may be $31, in which case nothing happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * The exception fixup information "just so happens" to be arranged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * as in a MEM format instruction.  This lets us emit our three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * values like so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *      lda valreg, nextinsn(errreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct exception_table_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	signed int insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	union exception_fixup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		unsigned unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			signed int nextinsn : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			unsigned int errreg : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			unsigned int valreg : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		} bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	} fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Returns the new pc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define fixup_exception(map_reg, _fixup, pc)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	if ((_fixup)->fixup.bits.valreg != 31)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		map_reg((_fixup)->fixup.bits.valreg) = 0;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	if ((_fixup)->fixup.bits.errreg != 31)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		map_reg((_fixup)->fixup.bits.errreg) = -EFAULT;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	(pc) + (_fixup)->fixup.bits.nextinsn;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ARCH_HAS_RELATIVE_EXTABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define swap_ex_entry_fixup(a, b, tmp, delta)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	do {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		(a)->fixup.unit = (b)->fixup.unit;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		(b)->fixup.unit = (tmp).fixup.unit;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif