^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * include/asm-alpha/dma.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * use ISA-compatible dma. The only extension is support for high-page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * registers that allow to set the top 8 bits of a 32-bit DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This register should be written last when setting up a DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * as this will also enable DMA across 64 KB boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * linux/include/asm/dma.h: Defines for using and allocating dma channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Written by Hennus Bergman, 1992.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * High DMA channel support & info by Hannu Savolainen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * and John Boyd, Nov. 1992.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef _ASM_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define _ASM_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define dma_outb outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define dma_inb inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * NOTES about DMA transfers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * controller 1: channels 0-3, byte operations, ports 00-1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * controller 2: channels 4-7, word operations, ports C0-DF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * - ALL registers are 8 bits only, regardless of transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - channel 4 is not used - cascades 1 into 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * - channels 0-3 are byte - addresses/counts are for physical bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * - channels 5-7 are word - addresses/counts are for physical words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - transfer count loaded to registers is 1 less than actual count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * - controller 2 offsets are all even (2x offsets for controller 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * - page registers for 5-7 don't use data bit 0, represent 128K pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - page registers for 0-3 use bit 0, represent 64K pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * DMA transfers are limited to the lower 16MB of _physical_ memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Note that addresses loaded into registers must be _physical_ addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * not logical addresses (which may differ if paging is active).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Address mapping for channels 0-3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * | ... | | ... | | ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * | ... | | ... | | ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * | ... | | ... | | ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * P7 ... P0 A7 ... A0 A7 ... A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * | Page | Addr MSB | Addr LSB | (DMA registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Address mapping for channels 5-7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * | ... | \ \ ... \ \ \ ... \ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * | ... | \ \ ... \ \ \ ... \ (not used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * | ... | \ \ ... \ \ \ ... \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * | Page | Addr MSB | Addr LSB | (DMA registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * the hardware level, so odd-byte transfers aren't possible).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Transfer count (_not # bytes_) is limited to 64K, represented as actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * and up to 128K bytes may be transferred on channels 5-7 in one operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAX_DMA_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ISA DMA limitations on Alpha platforms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) just a wiring limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* The maximum address for ISA DMA transfer on Alpha XL, due to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) hardware SIO limitation, is 64MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* The maximum address for ISA DMA transfer on RUFFIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) due to an hardware SIO limitation, is 16MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 0x01000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) due to an hardware SIO chip limitation, is 2GB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Maximum address for all the others is the complete 32-bit bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ALPHA_MAX_ISA_DMA_ADDRESS 0x100000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_ALPHA_GENERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # if defined(CONFIG_ALPHA_XL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define MAX_ISA_DMA_ADDRESS ALPHA_XL_MAX_ISA_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # elif defined(CONFIG_ALPHA_RUFFIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define MAX_ISA_DMA_ADDRESS ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # elif defined(CONFIG_ALPHA_SABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define MAX_ISA_DMA_ADDRESS ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # elif defined(CONFIG_ALPHA_ALCOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define MAX_ISA_DMA_ADDRESS ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* If we have the iommu, we don't have any address limitations on DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) like i386. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAX_DMA_ADDRESS (alpha_mv.mv_pci_tbi ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ~0UL : IDENT_ADDR + 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* 8237 DMA controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* DMA controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DMA1_CMD_REG 0x08 /* command register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DMA1_STAT_REG 0x08 /* status register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DMA1_REQ_REG 0x09 /* request register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DMA1_MODE_REG 0x0B /* mode register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DMA2_CMD_REG 0xD0 /* command register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DMA2_STAT_REG 0xD0 /* status register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DMA2_REQ_REG 0xD2 /* request register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DMA2_MODE_REG 0xD6 /* mode register (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DMA_ADDR_0 0x00 /* DMA address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DMA_ADDR_1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DMA_ADDR_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DMA_ADDR_3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DMA_ADDR_4 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DMA_ADDR_5 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DMA_ADDR_6 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DMA_ADDR_7 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DMA_CNT_0 0x01 /* DMA count registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DMA_CNT_1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DMA_CNT_2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DMA_CNT_3 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DMA_CNT_4 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DMA_CNT_5 0xC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DMA_CNT_6 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DMA_CNT_7 0xCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DMA_PAGE_0 0x87 /* DMA page registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DMA_PAGE_1 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DMA_PAGE_2 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DMA_PAGE_3 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DMA_PAGE_5 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DMA_PAGE_6 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DMA_PAGE_7 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DMA_AUTOINIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) extern spinlock_t dma_spin_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static __inline__ unsigned long claim_dma_lock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_lock_irqsave(&dma_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static __inline__ void release_dma_lock(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_unlock_irqrestore(&dma_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* enable/disable a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static __inline__ void enable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dma_outb(dmanr, DMA1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dma_outb(dmanr & 3, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static __inline__ void disable_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dma_outb(dmanr | 4, DMA1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Clear the 'DMA Pointer Flip Flop'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Write 0 for LSB/MSB, 1 for MSB/LSB access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Use this once to initialize the FF to a known state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * After that, keep track of it. :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * --- In order to do that, the DMA routines below should ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * --- only be used while interrupts are disabled! ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static __inline__ void clear_dma_ff(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dma_outb(0, DMA1_CLEAR_FF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dma_outb(0, DMA2_CLEAR_FF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* set mode (above) for a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dma_outb(mode | dmanr, DMA1_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* set extended mode for a specific DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (dmanr<=3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Set only the page register bits of the transfer address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * This is used for successive transfers when we know the contents of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * the lower 16 bits of the DMA current address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch(dmanr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma_outb(pagenr, DMA_PAGE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dma_outb((pagenr >> 8), DMA_HIPAGE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dma_outb(pagenr, DMA_PAGE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dma_outb((pagenr >> 8), DMA_HIPAGE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_outb(pagenr, DMA_PAGE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dma_outb((pagenr >> 8), DMA_HIPAGE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dma_outb(pagenr, DMA_PAGE_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dma_outb((pagenr >> 8), DMA_HIPAGE_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_outb(pagenr & 0xfe, DMA_PAGE_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dma_outb((pagenr >> 8), DMA_HIPAGE_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dma_outb(pagenr & 0xfe, DMA_PAGE_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dma_outb((pagenr >> 8), DMA_HIPAGE_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dma_outb(pagenr & 0xfe, DMA_PAGE_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_outb((pagenr >> 8), DMA_HIPAGE_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Set transfer address & page bits for specific DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Assumes dma flipflop is clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (dmanr <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * a specific DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * You must ensure the parameters are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * NOTE: from a manual: "the number of transfers is one more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * than the initial word count"! This is taken into account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Assumes dma flip-flop is clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (dmanr <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Get DMA residue count. After a DMA transfer, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * should return zero. Reading this while a DMA transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * still in progress will return unpredictable results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * If called before the channel has been used, it may return 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Otherwise, it returns the number of _bytes_ left to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Assumes DMA flip-flop is clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static __inline__ int get_dma_residue(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* using short to get 16-bit wrap around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned short count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) count = 1 + dma_inb(io_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) count += dma_inb(io_port) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return (dmanr<=3)? count : (count<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* These are in kernel/dma.c: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) extern void free_dma(unsigned int dmanr); /* release it again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define KERNEL_HAVE_CHECK_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) extern int check_dma(unsigned int dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* From PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) extern int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define isa_dma_bridge_buggy (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif /* _ASM_DMA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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