Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * include/asm-alpha/cache.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __ARCH_ALPHA_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __ARCH_ALPHA_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* Bytes per L1 (data) cache line. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) # define L1_CACHE_BYTES     64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) # define L1_CACHE_SHIFT     6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Both EV4 and EV5 are write-through, read-allocate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)    direct-mapped, physical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) # define L1_CACHE_BYTES     32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) # define L1_CACHE_SHIFT     5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SMP_CACHE_BYTES    L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif