Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) Atomic Operation Control (ATOMCTL) Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) We Have Atomic Operation Control (ATOMCTL) Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) This register determines the effect of using a S32C1I instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) with various combinations of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)      1. With and without an Coherent Cache Controller which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)         can do Atomic Transactions to the memory internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)      2. With and without An Intelligent Memory Controller which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)         can do Atomic Transactions itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The Core comes up with a default value of for the three types of cache ops::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)       0x28: (WB: Internal, WT: Internal, BY:Exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) On the FPGA Cards we typically simulate an Intelligent Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) which can implement  RCW transactions. For FPGA cards with an External
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Memory controller we let it to the atomic operations internally while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) doing a Cached (WB) transaction and use the Memory RCW for un-cached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) For systems without an coherent cache controller, non-MX, we always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) use the memory controllers RCW, thought non-MX controlers likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) support the Internal Operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CUSTOMER-WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)    Virtually all customers buy their memory controllers from vendors that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)    don't support atomic RCW memory transactions and will likely want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)    configure this register to not use RCW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Developers might find using RCW in Bypass mode convenient when testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) with the cache being bypassed; for example studying cache alias problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) See Section 4.3.12.4 of ISA; Bits::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)                              WB     WT      BY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)                            5   4 | 3   2 | 1   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) =========    ==================      ==================      ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   2 Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   Field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   Values     WB - Write Back         WT - Write Thru         BY - Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) =========    ==================      ==================      ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)     0        Exception               Exception               Exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     1        RCW Transaction         RCW Transaction         RCW Transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     2        Internal Operation      Internal Operation      Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)     3        Reserved                Reserved                Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) =========    ==================      ==================      ===============