Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) MPIC interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Device types supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Only one MPIC instance, of any type, may be instantiated.  The created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) MPIC will act as the system interrupt controller, connecting to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) vcpu's interrupt inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Groups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   KVM_DEV_MPIC_GRP_MISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       Base address of the 256 KiB MPIC register space.  Must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       naturally aligned.  A value of zero disables the mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       Reset value is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     Access an MPIC register, as if the access were made from the guest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     "attr" is the byte offset into the MPIC register space.  Accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     must be 4-byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     MSIs may be signaled by using this attribute group to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     to the relevant MSIIR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     IRQ input line for each standard openpic source.  0 is inactive and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)     is active, regardless of interrupt sense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)     For edge-triggered interrupts:  Writing 1 is considered an activating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)     edge, and writing 0 is ignored.  Reading returns 1 if a previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)     signaled edge has not been acknowledged, and 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)     "attr" is the IRQ number.  IRQ numbers for standard sources are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)     byte offset of the relevant IVPR from EIVPR0, divided by 32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IRQ Routing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   The MPIC emulation supports IRQ routing. Only a single MPIC device can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   be instantiated. Once that device has been created, it's available as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   irqchip id 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   This irqchip 0 has 256 interrupt pins, which expose the interrupts in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   the main array of interrupt sources (a.k.a. "SRC" interrupts).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   The numbering is the same as the MPIC device tree binding -- based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   the register offset from the beginning of the sources array, without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   regard to any subdivisions in chip documentation such as "internal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   or "external" interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.