^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ==============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ==============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Device types supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Only one VGIC instance may be instantiated through this API. The created VGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) will act as the VM interrupt controller, requiring emulated user-space devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) to inject interrupts to the VGIC instead of directly to CPUs. It is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) possible to create both a GICv3 and GICv2 on the same VM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Creating a guest GICv3 device requires a host GICv3 as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Groups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) KVM_DEV_ARM_VGIC_GRP_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Base address in the guest physical address space of the GICv3 distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) This address needs to be 64K aligned and the region covers 64 KByte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Base address in the guest physical address space of the GICv3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) redistributor register mappings. There are two 64K pages for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) VCPU and all of the redistributor pages are contiguous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) This address needs to be 64K aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) The attribute data pointed to by kvm_device_attr.addr is a __u64 value::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) values: | count | base | flags | index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - index encodes the unique redistributor region index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - flags: reserved for future use, currently 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - base field encodes bits [51:16] of the guest physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) of the first redistributor in the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - count encodes the number of redistributors in the region. Must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) greater than 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) There are two 64K pages for each redistributor in the region and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) redistributors are laid out contiguously within the region. Regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) are filled with redistributors in the index order. The sum of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) region count fields must be greater than or equal to the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) VCPUs. Redistributor regions must be registered in the incremental
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) index order, starting from index 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) The characteristics of a specific redistributor region can be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) by presetting the index field in the attr data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) It is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ======= =============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) -E2BIG Address outside of addressable IPA range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) -EINVAL Incorrectly aligned address, bad redistributor region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) count/index, mixed redistributor region attribute usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) -EEXIST Address already configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) -ENOENT Attempt to read the characteristics of a non existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) redistributor region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) -ENXIO The group or attribute is unknown/unsupported for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) or hardware support is missing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) -EFAULT Invalid user pointer for attr->addr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ======= =============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) The attr field of kvm_device_attr encodes two values::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bits: | 63 .... 32 | 31 .... 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) values: | mpidr | offset |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __u32 value. 64-bit registers must be accessed by separately accessing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) lower and higher word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) Writes to read-only registers are ignored by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) specified by the mpidr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) The offset is relative to the "[Re]Distributor base address" as defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) in the GICv3/4 specs. Getting or setting such a register has the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) effect as reading or writing the register on real hardware, except for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) differently when accessed via this interface compared to their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) architecturally defined behavior to allow software a full view of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) VGIC's internal state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) The mpidr field is used to specify which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) redistributor is accessed. The mpidr is ignored for the distributor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) The mpidr encoding is based on the affinity information in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) architecture defined MPIDR, and the field is encoded as follows::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | Aff3 | Aff2 | Aff1 | Aff0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Note that distributor fields are not banked, but return the same value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regardless of the mpidr used to access the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GICD_IIDR.Revision is updated when the KVM implementation is changed in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) way directly observable by the guest or userspace. Userspace should read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GICD_IIDR from KVM and write back the read value to confirm its expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) behavior is aligned with the KVM implementation. Userspace should set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GICD_IIDR before setting any other registers to ensure the expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) that a write of a clear bit has no effect, whereas a write with a set bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clears that value. To allow userspace to freely set the values of these two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) registers, setting the attributes with the register offsets for these two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) registers simply sets the non-reserved bits to the value written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Accesses (reads and writes) to the GICD_ISPENDR register region and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) GICR_ISPENDR0 registers get/set the value of the latched pending state for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) the interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) This is identical to the value returned by a guest read from ISPENDR for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) edge triggered interrupt, but may differ for level triggered interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) For edge triggered interrupts, once an interrupt becomes pending (whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) because of an edge detected on the input line or because of a guest write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) to ISPENDR) this state is "latched", and only cleared when either the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) interrupt is activated or when the guest writes to ICPENDR. A level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) triggered interrupt may be pending either because the level input is held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) high by a device, or because of a guest write to the ISPENDR register. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ISPENDR writes are latched; if the device lowers the line level then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) interrupt is no longer pending unless the guest also wrote to ISPENDR, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) conversely writes to ICPENDR or activations of the interrupt do not clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) the pending status if the line level is still being held high. (These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rules are documented in the GICv3 specification descriptions of the ICPENDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) and ISPENDR registers.) For a level triggered interrupt the value accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) interrupt activation, whereas the value returned by a guest read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ISPENDR is the logical OR of the latch value and the input line level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Raw access to the latch state is provided to userspace so that it can save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) and restore the entire GIC internal state (which is defined by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) combination of the current input line level and the latch state, and cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) be deduced from purely the line level and the value of the ISPENDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RAZ/WI semantics, meaning that reads always return 0 and writes are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) Errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ====== =====================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) -ENXIO Getting or setting this register is not yet supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) -EBUSY One or more VCPUs are running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ====== =====================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) The attr field of kvm_device_attr encodes two values::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bits: | 63 .... 32 | 31 .... 16 | 15 .... 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) values: | mpidr | RES | instr |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) The mpidr field encodes the CPU ID based on the affinity information in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) architecture defined MPIDR, and the field is encoded as follows::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) | Aff3 | Aff2 | Aff1 | Aff0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) The instr field encodes the system register to access based on the fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) defined in the A64 instruction set encoding for system register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (RES means the bits are reserved for future use and should be zero)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) | 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) | Op 0 | Op1 | CRn | CRm | Op2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) All system regs accessed through this API are (rw, 64-bit) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) kvm_device_attr.addr points to a __u64 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CPU specified by the mpidr field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CPU interface registers access is not implemented for AArch32 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) Error -ENXIO is returned when accessed in AArch32 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) Errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ======= =====================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) -ENXIO Getting or setting this register is not yet supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) -EBUSY VCPU is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) -EINVAL Invalid mpidr or register value supplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ======= =====================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) KVM_DEV_ARM_VGIC_GRP_NR_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) A value describing the number of interrupts (SGI, PPI and SPI) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) this GIC instance, ranging from 64 to 1024, in increments of 32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) kvm_device_attr.addr points to a __u32 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) Errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ======= ======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) -EINVAL Value set is out of the expected range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) -EBUSY Value has already be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ======= ======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) KVM_DEV_ARM_VGIC_GRP_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) KVM_DEV_ARM_VGIC_CTRL_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) request the initialization of the VGIC, no additional parameter in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kvm_device_attr.addr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) save all LPI pending bits into guest RAM pending tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) The first kB of the pending table is not altered by this operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) Errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ======= ========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) -ENXIO VGIC not properly configured as required prior to calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) this attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) -ENODEV no online VCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) -ENOMEM memory shortage when allocating vgic internal data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) -EFAULT Invalid guest ram access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) -EBUSY One or more VCPUS are running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ======= ========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) Attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) The attr field of kvm_device_attr encodes the following values::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bits: | 63 .... 32 | 31 .... 10 | 9 .... 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) values: | mpidr | info | vINTID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) The vINTID specifies which set of IRQs is reported on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) The info field specifies which information userspace wants to get or set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) using this interface. Currently we support the following info values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) VGIC_LEVEL_INFO_LINE_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) Get/Set the input level of the IRQ line for a set of 32 contiguously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) numbered interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) vINTID must be a multiple of 32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) kvm_device_attr.addr points to a __u32 value which will contain a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bitmap where a set bit means the interrupt level is asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) Bit[n] indicates the status for interrupt vINTID + n.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SGIs and any interrupt with a higher ID than the number of interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) supported, will be RAZ/WI. LPIs are always edge-triggered and are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) therefore not supported by this interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reported with the same value regardless of the mpidr specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) The mpidr field encodes the CPU ID based on the affinity information in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) architecture defined MPIDR, and the field is encoded as follows::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) | Aff3 | Aff2 | Aff1 | Aff0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) Errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ======= =============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) -EINVAL vINTID is not multiple of 32 or info field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) not VGIC_LEVEL_INFO_LINE_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ======= =============================================
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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