Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) .. _image-process-controls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) *******************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Image Process Control Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) *******************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The Image Process control class is intended for low-level control of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) image processing functions. Unlike ``V4L2_CID_IMAGE_SOURCE_CLASS``, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) controls in this class affect processing the image, and do not control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) capturing of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .. _image-process-control-id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Image Process Control IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ``V4L2_CID_IMAGE_PROC_CLASS (class)``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     The IMAGE_PROC class descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ``V4L2_CID_LINK_FREQ (integer menu)``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)     Data bus frequency. Together with the media bus pixel code, bus type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     (clock cycles per sample), the data bus frequency defines the pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     rate (``V4L2_CID_PIXEL_RATE``) in the pixel array (or possibly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     elsewhere, if the device is not an image sensor). The frame rate can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     be calculated from the pixel clock, image width and height and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)     horizontal and vertical blanking. While the pixel rate control may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     be defined elsewhere than in the subdev containing the pixel array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     the frame rate cannot be obtained from that information. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)     because only on the pixel array it can be assumed that the vertical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)     and horizontal blanking information is exact: no other blanking is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     allowed in the pixel array. The selection of frame rate is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)     by selecting the desired horizontal and vertical blanking. The unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     of this control is Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ``V4L2_CID_PIXEL_RATE (64-bit integer)``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)     Pixel rate in the source pads of the subdev. This control is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)     read-only and its unit is pixels / second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ``V4L2_CID_TEST_PATTERN (menu)``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)     Some capture/display/sensor devices have the capability to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)     test pattern images. These hardware specific test patterns can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     used to test if a device is working properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ``V4L2_CID_DEINTERLACING_MODE (menu)``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     The video deinterlacing mode (such as Bob, Weave, ...). The menu items are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     driver specific and are documented in :ref:`uapi-v4l-drivers`.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ``V4L2_CID_DIGITAL_GAIN (integer)``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     Digital gain is the value by which all colour components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)     are multiplied by. Typically the digital gain applied is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)     control value divided by e.g. 0x100, meaning that to get no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)     digital gain the control value needs to be 0x100. The no-gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)     configuration is also typically the default.