^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) spi_lm70llp : LM70-LLP parport-to-SPI adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Supported board/chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * National Semiconductor LM70 LLP evaluation board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Datasheet: http://www.national.com/pf/LM/LM70.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Kaiwan N Billimoria <kaiwan@designergraphix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) This driver provides glue code connecting a National Semiconductor LM70 LLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) temperature sensor evaluation board to the kernel's SPI core subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) This is a SPI master controller driver. It can be used in conjunction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) (layered under) the LM70 logical driver (a "SPI protocol driver").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) In effect, this driver turns the parallel port interface on the eval board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) into a SPI bus with a single device, which will be driven by the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) LM70 driver (drivers/hwmon/lm70.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Hardware Interfacing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) The schematic for this particular board (the LM70EVAL-LLP) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) available (on page 4) here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The hardware interfacing on the LM70 LLP eval board is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ======== == ========= ==========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Parallel LM70 LLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Port . Direction JP2 Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ======== == ========= ==========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) D0 2 - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) D1 3 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) D2 4 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) D3 5 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) D4 6 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) D5 7 --> nCS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) D6 8 --> SCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) D7 9 --> SI/O 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GND 25 - GND 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Select 13 <-- SI/O 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ======== == ========= ==========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) is connected to both pin D7 (as Master Out) and Select (as Master In)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) using an arrangement that lets either the parport or the LM70 pull the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pin low. This can't be shared with true SPI devices, but other 3-wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) devices might share the same SI/SO pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) The bitbanger routine in this driver (lm70_txrx) is called back from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) The lm70 driver then inteprets the resulting digital temperature value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) and exports it through sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) shows that the SI/O line from the LM70 chip is connected to the base of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) transistor Q1 (and also a pullup, and a zener diode to D7); while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) collector is tied to VCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Interpreting this circuit, when the LM70 SI/O line is High (or tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) and not grounded by the host via D7), the transistor conducts and switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) the collector to zero, which is reflected on pin 13 of the DB25 parport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) connector. When SI/O is Low (driven by the LM70 or the host) on the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) hand, the transistor is cut off and the voltage tied to it's collector is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reflected on pin 13 as a High level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) So: the getmiso inline routine in this driver takes this fact into account,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) inverting the value read at pin 13.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Thanks to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - David Brownell for mentoring the SPI-side driver development.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - Nadir Billimoria for help interpreting the circuit schematic.
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