^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) PXA2xx SPI on SSP driver HOWTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) synchronous serial port into a SPI master controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) (see Documentation/spi/spi-summary.rst). The driver has the following features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - Support for any PXA2xx SSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - SSP PIO and SSP DMA data transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - External and Internal (SSPFRM) chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - Per slave device (chip) configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - Full suspend, freeze, resume support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The driver is built around a "spi_message" fifo serviced by workqueue and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) (pump_transfer) is responsible for queuing SPI transactions and setting up and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) launching the dma/interrupt driven transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Declaring PXA2xx Master Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) -----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "platform device". The master configuration is passed to the driver via a table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) found in include/linux/spi/pxa2xx_spi.h::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct pxa2xx_spi_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 enable_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) slave device (chips) attached to this SPI master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) be used. This caused the driver to acquire two DMA channels: rx_channel and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) See the "PXA2xx Developer Manual" section "DMA Controller".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) NSSP MASTER SAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Below is a sample configuration using the PXA255 NSSP::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct resource pxa_spi_nssp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .start = IRQ_NSSP, /* NSSP IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .end = IRQ_NSSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct pxa2xx_spi_controller pxa_nssp_master_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .enable_dma = 1, /* Enables NSSP DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct platform_device pxa_spi_nssp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .resource = pxa_spi_nssp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .platform_data = &pxa_nssp_master_info, /* Passed to driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct platform_device *devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &pxa_spi_nssp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void __init board_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (void)platform_add_device(devices, ARRAY_SIZE(devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Declaring Slave Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) using the "spi_board_info" structure found in "linux/spi/spi.h". See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Documentation/spi/spi-summary.rst" for additional information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Each slave device attached to the PXA must provide slave specific configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) information via the structure "pxa2xx_spi_chip" found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) will uses the configuration whenever the driver communicates with the slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) device. All fields are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct pxa2xx_spi_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 tx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 rx_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 dma_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 enable_loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void (*cs_control)(u32 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) used to configure the SSP hardware fifo. These fields are critical to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) performance of pxa2xx_spi driver and misconfiguration will result in rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fifo overruns (especially in PIO mode transfers). Good default values are::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .tx_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .rx_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) The range is 1 to 16 where zero indicates "use default".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) engine and is related the "spi_device.bits_per_word" field. Read and understand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) to determine the correct value. An SSP configured for byte-wide transfers would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) use a value of 8. The driver will determine a reasonable default if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dma_burst_size == 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) trailing bytes in the SSP receiver fifo. The correct value for this field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) timeouts and must busy-wait any trailing bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) into internal loopback mode. In this mode the SSP controller internally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) function for asserting/deasserting a slave device chip select. If the field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) configured to use SSPFRM instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) chipselect is dropped after each spi_transfer. Most devices need chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) asserted around the complete message. Use SSPFRM as a GPIO (through cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) to accommodate these chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) NSSP SLAVE SAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "spi_board_info.controller_data" field. Below is a sample configuration using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) the PXA255 NSSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Chip Select control for the CS8415A SPI slave device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void cs8415a_cs_control(u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (command & PXA2XX_CS_ASSERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GPCR(2) = GPIO_bit(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GPSR(2) = GPIO_bit(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Chip Select control for the CS8405A SPI slave device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void cs8405a_cs_control(u32 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (command & PXA2XX_CS_ASSERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GPCR(3) = GPIO_bit(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GPSR(3) = GPIO_bit(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct pxa2xx_spi_chip cs8415a_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .tx_threshold = 8, /* SSP hardward FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .rx_threshold = 8, /* SSP hardward FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .timeout = 235, /* See Intel documentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .cs_control = cs8415a_cs_control, /* Use external chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct pxa2xx_spi_chip cs8405a_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .tx_threshold = 8, /* SSP hardward FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .rx_threshold = 8, /* SSP hardward FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .timeout = 235, /* See Intel documentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .cs_control = cs8405a_cs_control, /* Use external chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct spi_board_info streetracer_spi_board_info[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .modalias = "cs8415a", /* Name of spi_driver for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .bus_num = 2, /* Framework bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .chip_select = 0, /* Framework chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .platform_data = NULL; /* No spi_driver specific config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .controller_data = &cs8415a_chip_info, /* Master chip config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .modalias = "cs8405a", /* Name of spi_driver for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .bus_num = 2, /* Framework bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .chip_select = 1, /* Framework chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .controller_data = &cs8405a_chip_info, /* Master chip config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void __init streetracer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spi_register_board_info(streetracer_spi_board_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ARRAY_SIZE(streetracer_spi_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DMA and PIO I/O Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) transfers. The driver defaults to PIO mode and DMA transfers must be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mode supports both coherent and stream based DMA mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) The following logic is used to determine the type of I/O to be used on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) a per "spi_transfer" basis::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if !enable_dma then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) always use PIO transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if spi_message.len > 8191 then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) print "rate limited" warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) use PIO transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) use coherent DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if rx_buf and tx_buf are aligned on 8 byte boundary then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) use streaming DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) use PIO transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) THANKS TO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) David Brownell and others for mentoring the development of this driver.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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