Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ==================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ASoC Digital Audio Interface (DAI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ==================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) SoC controllers and portable audio CODECs today, namely AC97, I2S and PCM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) AC97 is a five wire interface commonly found on many PC sound cards. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) now also popular in many portable devices. This DAI has a reset line and time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) frame is 21uS long and is divided into 13 time slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The AC97 specification can be found at :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) https://www.intel.com/p/en_US/business/design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Rx lines are used for audio transmission, while the bit clock (BCLK) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) left/right clock (LRC) synchronise the link. I2S is flexible in that either the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) usually varies depending on the sample rate and the master system clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ADC and DAC LRCLKs, this allows for simultaneous capture and playback at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) different sample rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) I2S has several different operating modes:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   MSB is transmitted on the falling edge of the first BCLK after LRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Left Justified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   MSB is transmitted on transition of LRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Right Justified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   MSB is transmitted sample size BCLKs before LRC transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PCM is another 4 wire interface, very similar to I2S, which can support a more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) to synchronise the link while the Tx and Rx lines are used to transmit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) receive the audio data. Bit clock usually varies depending on sample rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) while sync runs at the sample rate. PCM also supports Time Division
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Multiplexing (TDM) in that several devices can use the bus simultaneously (this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) is sometimes referred to as network mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Common PCM operating modes:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Mode A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)   MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Mode B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   MSB is transmitted on rising edge of FRAME/SYNC.