Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) Audio Clocking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) This text describes the audio clocking terms in ASoC and digital audio in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) general. Note: Audio clocking can be complex!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Master Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) or SYSCLK). This audio master clock can be derived from a number of sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) audio playback and capture sample rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) their speed can be altered by software (depending on the system use and to save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) power). Other master clocks are fixed at a set frequency (i.e. crystals).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DAI Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The Digital Audio Interface is usually driven by a Bit Clock (often referred to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) as BCLK). This clock is used to drive the digital audio data across the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) between the codec and CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) The DAI also has a frame clock to signal the start of each audio frame. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) runs at exactly the sample rate (LRC = Rate).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Bit Clock can be generated as follows:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - BCLK = MCLK / x, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - BCLK = LRC * x, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - BCLK = LRC * Channels * Word Size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) This relationship depends on the codec or SoC CPU in particular. In general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) it is best to configure BCLK to the lowest possible speed (depending on your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) rate, number of channels and word size) to save on power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) It is also desirable to use the codec (if possible) to drive (or master) the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) audio clocks as it usually gives more accurate sample rates than the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)