Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Notes on register bank usage in the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The SH-3 and SH-4 CPU families traditionally include a single partial register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) may have more full-featured banking or simply no such capabilities at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SR.RB banking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) In the case of this type of banking, banked registers are mapped directly to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) can still be used to reference the banked registers (as r0_bank ... r7_bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) when in the context of another bank. The developer must keep the SR.RB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) in mind when writing code that utilizes these banked registers, for obvious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reasons. Userspace is also not able to poke at the bank1 values, so these can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) be used rather effectively as scratch registers by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Presently the kernel uses several of these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	- r0_bank, r1_bank (referenced as k0 and k1, used for scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	  registers when doing exception handling).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	- r2_bank (used to track the EXPEVT/INTEVT code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		- Used by do_IRQ() and friends for doing irq mapping based off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		  of the interrupt exception vector jump table offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	- r6_bank (global interrupt mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		- The SR.IMASK interrupt handler makes use of this to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		  interrupt priority level (used by local_irq_enable())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	- r7_bank (current)