^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The 53c700 Driver Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) General Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) This driver supports the 53c700 and 53c700-66 chips. It also supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the 53c710 but only in 53c700 emulation mode. It is full featured and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) does sync (-66 and 710 only), disconnects and tag command queueing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Since the 53c700 must be interfaced to a bus, you need to wrapper the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) card detector around this driver. For an example, see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) NCR_D700.[ch] or lasi700.[ch] files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) The comments in the 53c700.[ch] files tell you which parts you need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) fill in to get the driver working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Compile Time Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) A compile time flag is::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CONFIG_53C700_LE_ON_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) define if the chipset must be supported in little endian mode on a big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) endian architecture (used for the 700 on parisc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Using the Chip Core Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ==========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) In order to plumb the 53c700 chip core driver into a working SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) driver, you need to know three things about the way the chip is wired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) into your system (or expansion card).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1. The clock speed of the SCSI core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 2. The interrupt line used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 3. The memory (or io space) location of the 53c700 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Optionally, you may also need to know other things, like how to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) the SCSI Id from the card bios or whether the chip is wired for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) differential operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Usually you can find items 2. and 3. from general spec. documents or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) even by examining the configuration of a working driver under another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) operating system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) The clock speed is usually buried deep in the technical literature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) It is required because it is used to set up both the synchronous and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) asynchronous dividers for the chip. As a general rule of thumb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) manufacturers set the clock speed at the lowest possible setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) consistent with the best operation of the chip (although some choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) to drive it off the CPU or bus clock rather than going to the expense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) of an extra clock chip). The best operation clock speeds are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ========= =====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 53c700 25MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 53c700-66 50MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 53c710 40Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ========= =====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Writing Your Glue Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) This will be a standard SCSI driver (I don't know of a good document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) describing this, just copy from some other driver) with at least a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) detect and release entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) In the detect routine, you need to allocate a struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) NCR_700_Host_Parameters sized memory area and clear it (so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) default values for everything are 0). Then you must fill in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) parameters that matter to you (see below), plumb the NCR_700_intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) routine into the interrupt line and call NCR_700_detect with the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) template and the new parameters as arguments. You should also call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) the relevant request_*_region function and place the register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) address into the 'base' pointer of the host parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) In the release routine, you must free the NCR_700_Host_Parameters that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) you allocated, call the corresponding release_*_region and free the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Handling Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) In general, you should just plumb the card's interrupt line in with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) request_irq(irq, NCR_700_intr, <irq flags>, <driver name>, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) where host is the return from the relevant NCR_700_detect() routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) You may also write your own interrupt handling routine which calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) NCR_700_intr() directly. However, you should only really do this if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) you have a card with more than one chip on it and you can read a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) register to tell which set of chips wants the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Settable NCR_700_Host_Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) --------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) The following are a list of the user settable parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clock: (MANDATORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Set to the clock speed of the chip in MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) base: (MANDATORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Set to the base of the io or mem region for the register set. On 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bit architectures this is only 32 bits wide, so the registers must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mapped into the low 32 bits of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pci_dev: (OPTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Set to the PCI board device. Leave NULL for a non-pci board. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) used for the pci_alloc_consistent() and pci_map_*() functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dmode_extra: (OPTIONAL, 53c710 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Extra flags for the DMODE register. These are used to control bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) output pins on the 710. The settings should be a combination of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DMODE_FC1 and DMODE_FC2. What these pins actually do is entirely up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) to the board designer. Usually it is safe to ignore this setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) differential: (OPTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) Set to 1 if the chip drives a differential bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) force_le_on_be: (OPTIONAL, only if CONFIG_53C700_LE_ON_BE is set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) Set to 1 if the chip is operating in little endian mode on a big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) endian architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) chip710: (OPTIONAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Set to 1 if the chip is a 53c710.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) burst_disable: (OPTIONAL, 53c710 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) Disable 8 byte bursting for DMA transfers.
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