^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Freescale QUICC Engine Firmware Uploading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) (c) 2007 Timur Tabi <timur at freescale.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Freescale Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) .. Table of Contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) I - Software License for Firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) II - Microcode Availability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) III - Description and Terminology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) IV - Microcode Programming Details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) V - Firmware Structure Layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) VI - Sample Code for Creating Firmware Files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Revision Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) November 30, 2007: Rev 1.0 - Initial version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) I - Software License for Firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Each firmware file comes with its own software license. For information on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the particular license, please see the license text that is distributed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) II - Microcode Availability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ===========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Firmware files are distributed through various channels. Some are available on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) http://opensource.freescale.com. For other firmware files, please contact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) your Freescale representative or your operating system vendor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) III - Description and Terminology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) In this document, the term 'microcode' refers to the sequence of 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) integers that compose the actual QE microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) The term 'firmware' refers to a binary blob that contains the microcode as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) well as other data that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1) describes the microcode's purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 2) describes how and where to upload the microcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 3) specifies the values of various registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 4) includes additional data for use by specific device drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Firmware files are binary files that contain only a firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IV - Microcode Programming Details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ===================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) The QE architecture allows for only one microcode present in I-RAM for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RISC processor. To replace any current microcode, a full QE reset (which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) disables the microcode) must be performed first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) QE microcode is uploaded using the following procedure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1) The microcode is placed into I-RAM at a specific location, using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) IRAM.IADD and IRAM.IDATA registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 2) The CERCR.CIR bit is set to 0 or 1, depending on whether the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) needs split I-RAM. Split I-RAM is only meaningful for SOCs that have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) QEs with multiple RISC processors, such as the 8360. Splitting the I-RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) allows each processor to run a different microcode, effectively creating an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) asymmetric multiprocessing (AMP) system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 3) The TIBCR trap registers are loaded with the addresses of the trap handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) in the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 4) The RSP.ECCR register is programmed with the value provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 5) If necessary, device drivers that need the virtual traps and extended mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) data will use them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Virtual Microcode Traps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) These virtual traps are conditional branches in the microcode. These are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "soft" provisional introduced in the ROMcode in order to enable higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) flexibility and save h/w traps If new features are activated or an issue is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) being fixed in the RAM package utilizing they should be activated. This data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) structure signals the microcode which of these virtual traps is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) This structure contains 6 words that the application should copy to some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) specific been defined. This table describes the structure::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) | Offset in | | Destination Offset | Size of |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) | array | Protocol | within PRAM | Operand |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) --------------------------------------------------------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) | 0 | Ethernet | 0xF8 | 4 bytes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) | | interworking | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) | 4 | ATM | 0xF8 | 4 bytes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) | | interworking | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | 8 | PPP | 0xF8 | 4 bytes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) | | interworking | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) | 12 | Ethernet RX | 0x22 | 1 byte |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) | | Distributor Page | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | 16 | ATM Globtal | 0x28 | 1 byte |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | | Params Table | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) | 20 | Insert Frame | 0xF8 | 4 bytes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) Extended Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) This is a double word bit array (64 bits) that defines special functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) which has an impact on the software drivers. Each bit has its own impact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) and has special instructions for the s/w associated with it. This structure is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) described in this table::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | Bit # | Name | Description |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | 0 | General | Indicates that prior to each host command |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | | push command | given by the application, the software must |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) | | | assert a special host command (push command)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) | | | CECDR = 0x00800000. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | | | CECR = 0x01c1000f. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | 1 | UCC ATM | Indicates that after issuing ATM RX INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) | | RX INIT | command, the host must issue another special|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) | | push command | command (push command) and immediately |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | | | following that re-issue the ATM RX INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | | | command. (This makes the sequence of |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) | | | initializing the ATM receiver a sequence of |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) | | | three host commands) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) | | | CECDR = 0x00800000. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) | | | CECR = 0x01c1000f. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) | 2 | Add/remove | Indicates that following the specific host |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) | | command | command: "Add/Remove entry in Hash Lookup |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) | | validation | Table" used in Interworking setup, the user |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) | | | must issue another command. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) | | | CECDR = 0xce000003. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) | | | CECR = 0x01c10f58. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) | 3 | General push | Indicates that the s/w has to initialize |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) | | command | some pointers in the Ethernet thread pages |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) | | | which are used when Header Compression is |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) | | | activated. The full details of these |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) | | | pointers is located in the software drivers.|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) | 4 | General push | Indicates that after issuing Ethernet TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) | | command | INIT command, user must issue this command |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) | | | for each SNUM of Ethernet TX thread. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) | | | CECDR = 0x00800003. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) | | | CECR = 0x7'b{0}, 8'b{Enet TX thread SNUM}, |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) | | | 1'b{1}, 12'b{0}, 4'b{1} |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) | 5 - 31 | N/A | Reserved, set to zero. |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) V - Firmware Structure Layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) QE microcode from Freescale is typically provided as a header file. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) header file contains macros that define the microcode binary itself as well as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) some other data used in uploading that microcode. The format of these files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) do not lend themselves to simple inclusion into other code. Hence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) the need for a more portable format. This section defines that format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) Instead of distributing a header file, the microcode and related data are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) embedded into a binary blob. This blob is passed to the qe_upload_firmware()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) function, which parses the blob and performs everything necessary to upload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) All integers are big-endian. See the comments for function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) qe_upload_firmware() for up-to-date implementation information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) This structure supports versioning, where the version of the structure is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) embedded into the structure itself. To ensure forward and backwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) compatibility, all versions of the structure must use the same 'qe_header'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) structure at the beginning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 'header' (type: struct qe_header):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) The 'length' field is the size, in bytes, of the entire structure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) including all the microcode embedded in it, as well as the CRC (if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) present).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) The 'magic' field is an array of three bytes that contains the letters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 'Q', 'E', and 'F'. This is an identifier that indicates that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) structure is a QE Firmware structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) The 'version' field is a single byte that indicates the version of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) structure. If the layout of the structure should ever need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) changed to add support for additional types of microcode, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) version number should also be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) The 'id' field is a null-terminated string(suitable for printing) that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) identifies the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) The 'count' field indicates the number of 'microcode' structures. There
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) must be one and only one 'microcode' structure for each RISC processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) Therefore, this field also represents the number of RISC processors for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) The 'soc' structure contains the SOC numbers and revisions used to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) the microcode to the SOC itself. Normally, the microcode loader should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) check the data in this structure with the SOC number and revisions, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) only upload the microcode if there's a match. However, this check is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) made on all platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) Although it is not recommended, you can specify '0' in the soc.model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) field to skip matching SOCs altogether.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) The 'model' field is a 16-bit number that matches the actual SOC. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 'major' and 'minor' fields are the major and minor revision numbers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) respectively, of the SOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) For example, to match the 8323, revision 1.0::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) soc.model = 8323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) soc.major = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) soc.minor = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 'padding' is necessary for structure alignment. This field ensures that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 'extended_modes' field is aligned on a 64-bit boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 'extended_modes' is a bitfield that defines special functionality which has an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) impact on the device drivers. Each bit has its own impact and has special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) instructions for the driver associated with it. This field is stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) the QE library and available to any driver that calles qe_get_firmware_info().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 'vtraps' is an array of 8 words that contain virtual trap values for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) virtual traps. As with 'extended_modes', this field is stored in the QE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) library and available to any driver that calles qe_get_firmware_info().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 'microcode' (type: struct qe_microcode):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) For each RISC processor there is one 'microcode' structure. The first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 'microcode' structure is for the first RISC, and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) The 'id' field is a null-terminated string suitable for printing that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) identifies this particular microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 'traps' is an array of 16 words that contain hardware trap values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for each of the 16 traps. If trap[i] is 0, then this particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) trap is to be ignored (i.e. not written to TIBCR[i]). The entire value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) is written as-is to the TIBCR[i] register, so be sure to set the EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) and T_IBP bits if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 'eccr' is the value to program into the ECCR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 'iram_offset' is the offset into IRAM to start writing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 'count' is the number of 32-bit words in the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 'code_offset' is the offset, in bytes, from the beginning of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) structure where the microcode itself can be found. The first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) microcode binary should be located immediately after the 'microcode'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 'major', 'minor', and 'revision' are the major, minor, and revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) version numbers, respectively, of the microcode. If all values are 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) then these fields are ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 'reserved' is necessary for structure alignment. Since 'microcode'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) is an array, the 64-bit 'extended_modes' field needs to be aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) on a 64-bit boundary, and this can only happen if the size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 'microcode' is a multiple of 8 bytes. To ensure that, we add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 'reserved'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) After the last microcode is a 32-bit CRC. It can be calculated using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) this algorithm::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 crc32(const u8 *p, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 crc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) crc ^= *p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) VI - Sample Code for Creating Firmware Files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) A Python program that creates firmware binaries from the header files normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) distributed by Freescale can be found on http://opensource.freescale.com.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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