Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) ======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) Ptrace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) ======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) GDB intends to support the following hardware debug features of BookE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) processors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 4 hardware breakpoints (IAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 2 hardware watchpoints (read, write and read-write) (DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 2 value conditions for the hardware watchpoints (DVC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) For that, we need to extend ptrace so that GDB can query and set these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) resources. Since we're extending, we're trying to create an interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) that's extendable and that covers both BookE and server processors, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) that GDB doesn't need to special-case each of them. We added the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) following 3 new ptrace requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 1. PTRACE_PPC_GETHWDEBUGINFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) Query for GDB to discover the hardware debug features. The main info to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) be returned here is the minimum alignment for the hardware watchpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) BookE processors don't have restrictions here, but server processors have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) adding special cases to GDB based on what it sees in AUXV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) Since we're at it, we added other useful info that the kernel can return to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) GDB: this query will return the number of hardware breakpoints, hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) watchpoints and whether it supports a range of addresses and a condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) The query will fill the following structure provided by the requesting process::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)   struct ppc_debug_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)        unit32_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)        unit32_t num_instruction_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)        unit32_t num_data_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)        unit32_t num_condition_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)        unit32_t data_bp_alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)        unit32_t sizeof_condition; /* size of the DVC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)        uint64_t features; /* bitmask of the individual flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)   };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) features will have bits indicating whether there is support for::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)   #define PPC_DEBUG_FEATURE_INSN_BP_RANGE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)   #define PPC_DEBUG_FEATURE_INSN_BP_MASK		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)   #define PPC_DEBUG_FEATURE_DATA_BP_RANGE		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)   #define PPC_DEBUG_FEATURE_DATA_BP_MASK		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)   #define PPC_DEBUG_FEATURE_DATA_BP_DAWR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)   #define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 2. PTRACE_SETHWDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) Sets a hardware breakpoint or watchpoint, according to the provided structure::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)   struct ppc_hw_breakpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)         uint32_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)   #define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)   #define PPC_BREAKPOINT_TRIGGER_READ     0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  #define PPC_BREAKPOINT_TRIGGER_WRITE    0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)         uint32_t trigger_type;       /* only some combinations allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)   #define PPC_BREAKPOINT_MODE_EXACT               0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)   #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)   #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)   #define PPC_BREAKPOINT_MODE_MASK                0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)         uint32_t addr_mode;          /* address match mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)   #define PPC_BREAKPOINT_CONDITION_MODE   0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)   #define PPC_BREAKPOINT_CONDITION_NONE   0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)   #define PPC_BREAKPOINT_CONDITION_AND    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)   #define PPC_BREAKPOINT_CONDITION_EXACT  0x1	/* different name for the same thing as above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)   #define PPC_BREAKPOINT_CONDITION_OR     0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)   #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)   #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000	/* byte enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)   #define PPC_BREAKPOINT_CONDITION_BE(n)  (1<<((n)+16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)         uint32_t condition_mode;     /* break/watchpoint condition flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)         uint64_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)         uint64_t addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)         uint64_t condition_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)   };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) A request specifies one event, not necessarily just one register to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) For instance, if the request is for a watchpoint with a condition, both the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) DAC and DVC registers will be set in the same request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) With this GDB can ask for all kinds of hardware breakpoints and watchpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) that the BookE supports. COMEFROM breakpoints available in server processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) are not contemplated, but that is out of the scope of this work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) ptrace will return an integer (handle) uniquely identifying the breakpoint or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) request to ask for its removal. Return -ENOSPC if the requested breakpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) can't be allocated on the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) Some examples of using the structure to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) - set a breakpoint in the first breakpoint register::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)     p.version         = PPC_DEBUG_CURRENT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)     p.trigger_type    = PPC_BREAKPOINT_TRIGGER_EXECUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)     p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)     p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)     p.addr            = (uint64_t) address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)     p.addr2           = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)     p.condition_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - set a watchpoint which triggers on reads in the second watchpoint register::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)     p.version         = PPC_DEBUG_CURRENT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)     p.trigger_type    = PPC_BREAKPOINT_TRIGGER_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)     p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)     p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)     p.addr            = (uint64_t) address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)     p.addr2           = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)     p.condition_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - set a watchpoint which triggers only with a specific value::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)     p.version         = PPC_DEBUG_CURRENT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)     p.trigger_type    = PPC_BREAKPOINT_TRIGGER_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)     p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)     p.condition_mode  = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)     p.addr            = (uint64_t) address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)     p.addr2           = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)     p.condition_value = (uint64_t) condition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) - set a ranged hardware breakpoint::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)     p.version         = PPC_DEBUG_CURRENT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)     p.trigger_type    = PPC_BREAKPOINT_TRIGGER_EXECUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)     p.addr_mode       = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)     p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)     p.addr            = (uint64_t) begin_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)     p.addr2           = (uint64_t) end_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)     p.condition_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) - set a watchpoint in server processors (BookS)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)     p.version         = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)     p.trigger_type    = PPC_BREAKPOINT_TRIGGER_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)     p.addr_mode       = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)     or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)     p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)     p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)     p.addr            = (uint64_t) begin_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)     /* For PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE addr2 needs to be specified, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)      * addr2 - addr <= 8 Bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)     p.addr2           = (uint64_t) end_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)     p.condition_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 3. PTRACE_DELHWDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) Takes an integer which identifies an existing breakpoint or watchpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) corresponding breakpoint or watchpoint..