^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ===================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) DSCR (Data Stream Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ===================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) DSCR register in powerpc allows user to have some control of prefetch of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) stream in the processor. Please refer to the ISA documents or related manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) for more detailed information regarding how to use this DSCR to attain this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) control of the prefetches . This document here provides an overview of kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) support for DSCR, related kernel objects, it's functionalities and exported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) user interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) (A) Data Structures:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) (1) thread_struct::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) dscr /* Thread DSCR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) dscr_inherit /* Thread has changed default DSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) (2) PACA::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) dscr_default /* per-CPU DSCR default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) (3) sysfs.c::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) dscr_default /* System DSCR default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (B) Scheduler Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Scheduler will write the per-CPU DSCR default which is stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CPU's PACA value into the register if the thread has dscr_inherit value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) cleared which means that it has not changed the default DSCR till now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) If the dscr_inherit value is set which means that it has changed the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) default DSCR value, scheduler will write the changed value which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) now be contained in thread struct's dscr into the register instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) the per-CPU default PACA based DSCR value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) NOTE: Please note here that the system wide global DSCR value never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) gets used directly in the scheduler process context switch at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (C) SYSFS Interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - Global DSCR default: /sys/devices/system/cpu/dscr_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Changing the global DSCR default in the sysfs will change all the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) specific DSCR defaults immediately in their PACA structures. Again if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) the current process has the dscr_inherit clear, it also writes the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) value into every CPU's DSCR register right away and updates the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) thread's DSCR value as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Changing the CPU specific DSCR default value in the sysfs does exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) the same thing as above but unlike the global one above, it just changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) stuff for that particular CPU instead for all the CPUs on the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (D) User Space Instructions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) The DSCR register can be accessed in the user space using any of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) two SPR numbers available for that purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (2) Privileged state SPR: 0x11 (Privileged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Accessing DSCR through privileged SPR number (0x11) from user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) works, as it is emulated following an illegal instruction exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) inside the kernel. Both mfspr and mtspr instructions are emulated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Accessing DSCR through user level SPR (0x03) from user space will first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) create a facility unavailable exception. Inside this exception handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) all mfspr instruction based read attempts will get emulated and returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) where as the first mtspr instruction based write attempts will enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) the DSCR facility for the next time around (both for read and write) by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) setting DSCR facility in the FSCR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (E) Specifics about 'dscr_inherit':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) The thread struct element 'dscr_inherit' represents whether the thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) in question has attempted and changed the DSCR itself using any of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) following methods. This element signifies whether the thread wants to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) use the CPU default DSCR value or its own changed DSCR value in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (1) mtspr instruction (SPR number 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (2) mtspr instruction (SPR number 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (3) ptrace interface (Explicitly set user DSCR value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Any child of the process created after this event in the process inherits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) this same behaviour as well.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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