Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) PA-RISC Debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) okay, here are some hints for debugging the lower-level parts of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) linux/parisc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 1. Absolute addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) A lot of the assembly code currently runs in real mode, which means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) absolute addresses are used instead of virtual addresses as in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) rest of the kernel.  To translate an absolute address to a virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) address you can lookup in System.map, add __PAGE_OFFSET (0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) currently).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 2. HPMCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) When real-mode code tries to access non-existent memory, you'll get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) an HPMC instead of a kernel oops.  To debug an HPMC, try to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) the System Responder/Requestor addresses.  The System Requestor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) address should match (one of the) processor HPAs (high addresses in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) the I/O range); the System Responder address is the address real-mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) code tried to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Typical values for the System Responder address are addresses larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) get translated to a physical address before real-mode code tried to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) access it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 3. Q bit fun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Certain, very critical code has to clear the Q bit in the PSW.  What
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) happens when the Q bit is cleared is the CPU does not update the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) registers interruption handlers read to find out where the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) was interrupted - so if you get an interruption between the instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) that clears the Q bit and the RFI that sets it again you don't know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) where exactly it happened.  If you're lucky the IAOQ will point to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) instruction that cleared the Q bit, if you're not it points anywhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) at all.  Usually Q bit problems will show themselves in unexplainable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) system hangs or running off the end of physical memory.