^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) NXP SJA1105 switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) The NXP SJA1105 is a family of 6 devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - SJA1105E: First generation, no TTEthernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - SJA1105T: First generation, TTEthernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - SJA1105P: Second generation, no TTEthernet, no SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - SJA1105Q: Second generation, TTEthernet, no SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - SJA1105R: Second generation, no TTEthernet, SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - SJA1105S: Second generation, TTEthernet, SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) These are SPI-managed automotive switches, with all ports being gigabit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) capable, and supporting MII/RMII/RGMII and optionally SGMII on one port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Being automotive parts, their configuration interface is geared towards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) set-and-forget use, with minimal dynamic interaction at runtime. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) require a static configuration to be composed by software and packed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) with CRC and table headers, and sent over SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) The static configuration is composed of several configuration tables. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) table takes a number of entries. Some configuration tables can be (partially)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) reconfigured at runtime, some not. Some tables are mandatory, some not:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ============================= ================== =============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Table Mandatory Reconfigurable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ============================= ================== =============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Schedule no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Schedule entry points if Scheduling no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) VL Lookup no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) VL Policing if VL Lookup no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) VL Forwarding if VL Lookup no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) L2 Lookup no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) L2 Policing yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) VLAN Lookup yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) L2 Forwarding yes partially (fully on P/Q/R/S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MAC Config yes partially (fully on P/Q/R/S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Schedule Params if Scheduling no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Schedule Entry Points Params if Scheduling no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) VL Forwarding Params if VL Forwarding no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) L2 Lookup Params no partially (fully on P/Q/R/S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) L2 Forwarding Params yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Clock Sync Params no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) AVB Params no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) General Params yes partially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Retagging no yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) xMII Params yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SGMII no yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ============================= ================== =============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Also the configuration is write-only (software cannot read it back from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch except for very few exceptions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) The driver creates a static configuration at probe time, and keeps it at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) all times in memory, as a shadow for the hardware state. When required to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) change a hardware setting, the static configuration is also updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) If that changed setting can be transmitted to the switch through the dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reconfiguration interface, it is; otherwise the switch is reset and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reprogrammed with the updated static configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Traffic support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) The switches do not have hardware support for DSA tags, except for "slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) protocols" for switch control as STP and PTP. For these, the switches have two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) programmable filters for link-local destination MACs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) These are used to trap BPDUs and PTP traffic to the master netdevice, and are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) further used to support STP and 1588 ordinary clock/boundary clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) functionality. For frames trapped to the CPU, source port and switch ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) information is encoded by the hardware into the frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) But by leveraging ``CONFIG_NET_DSA_TAG_8021Q`` (a software-defined DSA tagging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) format based on VLANs), general-purpose traffic termination through the network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) stack can be supported under certain circumstances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Depending on VLAN awareness state, the following operating modes are possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) with the switch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - Mode 1 (VLAN-unaware): a port is in this mode when it is used as a standalone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) net device, or when it is enslaved to a bridge with ``vlan_filtering=0``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - Mode 2 (fully VLAN-aware): a port is in this mode when it is enslaved to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bridge with ``vlan_filtering=1``. Access to the entire VLAN range is given to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) the user through ``bridge vlan`` commands, but general-purpose (anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) other than STP, PTP etc) traffic termination is not possible through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch net devices. The other packets can be still by user space processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) through the DSA master interface (similar to ``DSA_TAG_PROTO_NONE``).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - Mode 3 (best-effort VLAN-aware): a port is in this mode when enslaved to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bridge with ``vlan_filtering=1``, and the devlink property of its parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch named ``best_effort_vlan_filtering`` is set to ``true``. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) configured like this, the range of usable VIDs is reduced (0 to 1023 and 3072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) to 4094), so is the number of usable VIDs (maximum of 7 non-pvid VLANs per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) port*), and shared VLAN learning is performed (FDB lookup is done only by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DMAC, not also by VID).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) To summarize, in each mode, the following types of traffic are supported over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) the switch net devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) +-------------+-----------+--------------+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | | Mode 1 | Mode 2 | Mode 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) +=============+===========+==============+============+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) | Regular | Yes | No | Yes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) | traffic | | (use master) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) +-------------+-----------+--------------+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) | Management | Yes | Yes | Yes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | traffic | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | (BPDU, PTP) | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) +-------------+-----------+--------------+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) To configure the switch to operate in Mode 3, the following steps can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) followed::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ip link add dev br0 type bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # swp2 operates in Mode 1 now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ip link set dev swp2 master br0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # swp2 temporarily moves to Mode 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ip link set dev br0 type bridge vlan_filtering 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [ 61.204770] sja1105 spi0.1: Reset switch and programmed static config. Reason: VLAN filtering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [ 61.239944] sja1105 spi0.1: Disabled switch tagging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # swp3 now operates in Mode 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) devlink dev param set spi/spi0.1 name best_effort_vlan_filtering value true cmode runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [ 64.682927] sja1105 spi0.1: Reset switch and programmed static config. Reason: VLAN filtering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [ 64.711925] sja1105 spi0.1: Enabled switch tagging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # Cannot use VLANs in range 1024-3071 while in Mode 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bridge vlan add dev swp2 vid 1025 untagged pvid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RTNETLINK answers: Operation not permitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bridge vlan add dev swp2 vid 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bridge vlan add dev swp2 vid 101 untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bridge vlan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) port vlan ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) swp5 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) swp2 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 101 Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) swp3 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) swp4 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) br0 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bridge vlan add dev swp2 vid 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bridge vlan add dev swp2 vid 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bridge vlan add dev swp2 vid 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bridge vlan add dev swp2 vid 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bridge vlan add dev swp2 vid 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bridge vlan add dev swp2 vid 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # Cannot use mode than 7 VLANs per port while in Mode 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [ 3885.216832] sja1105 spi0.1: No more free subvlans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) \* "maximum of 7 non-pvid VLANs per port": Decoding VLAN-tagged packets on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CPU in mode 3 is possible through VLAN retagging of packets that go from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) switch to the CPU. In cross-chip topologies, the port that goes to the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) might also go to other switches. In that case, those other switches will see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) only a retagged packet (which only has meaning for the CPU). So if they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) interested in this VLAN, they need to apply retagging in the reverse direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) to recover the original value from it. This consumes extra hardware resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for this switch. There is a maximum of 32 entries in the Retagging Table of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) each switch device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) As an example, consider this cross-chip topology::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) +-------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) | Host SoC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | +-------------------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | | DSA master for embedded | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) | | switch (non-sja1105) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) | +--------+-------------------------+--------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) | | embedded L2 switch | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) | | +--------------+ +--------------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) | | |DSA master for| |DSA master for| | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) | | | SJA1105 1 | | SJA1105 2 | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) +--+---+--------------+-----+--------------+---+--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) +-----------------------+ +-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) | SJA1105 switch 1 | | SJA1105 switch 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) +-----+-----+-----+-----+ +-----+-----+-----+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) |sw1p0|sw1p1|sw1p2|sw1p3| |sw2p0|sw2p1|sw2p2|sw2p3|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) +-----+-----+-----+-----+ +-----+-----+-----+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) To reach the CPU, SJA1105 switch 1 (spi/spi2.1) uses the same port as is uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) to reach SJA1105 switch 2 (spi/spi2.2), which would be port 4 (not drawn).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Similarly for SJA1105 switch 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) Also consider the following commands, that add VLAN 100 to every sja1105 user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) port::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) devlink dev param set spi/spi2.1 name best_effort_vlan_filtering value true cmode runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) devlink dev param set spi/spi2.2 name best_effort_vlan_filtering value true cmode runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ip link add dev br0 type bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for port in sw1p0 sw1p1 sw1p2 sw1p3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sw2p0 sw2p1 sw2p2 sw2p3; do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ip link set dev $port master br0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ip link set dev br0 type bridge vlan_filtering 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for port in sw1p0 sw1p1 sw1p2 sw1p3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sw2p0 sw2p1 sw2p2; do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bridge vlan add dev $port vid 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ip link add link br0 name br0.100 type vlan id 100 && ip link set dev br0.100 up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ip addr add 192.168.100.3/24 dev br0.100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bridge vlan add dev br0 vid 100 self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bridge vlan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) port vlan ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sw1p0 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sw1p1 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sw1p2 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sw1p3 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sw2p0 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sw2p1 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sw2p2 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sw2p3 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) br0 1 PVID Egress Untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SJA1105 switch 1 consumes 1 retagging entry for each VLAN on each user port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) towards the CPU. It also consumes 1 retagging entry for each non-pvid VLAN that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) it is also interested in, which is configured on any port of any neighbor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) In this case, SJA1105 switch 1 consumes a total of 11 retagging entries, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) - 8 retagging entries for VLANs 1 and 100 installed on its user ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (``sw1p0`` - ``sw1p3``)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) - 3 retagging entries for VLAN 100 installed on the user ports of SJA1105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch 2 (``sw2p0`` - ``sw2p2``), because it also has ports that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) interested in it. The VLAN 1 is a pvid on SJA1105 switch 2 and does not need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reverse retagging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SJA1105 switch 2 also consumes 11 retagging entries, but organized as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) - 7 retagging entries for the bridge VLANs on its user ports (``sw2p0`` -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ``sw2p3``).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) - 4 retagging entries for VLAN 100 installed on the user ports of SJA1105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch 1 (``sw1p0`` - ``sw1p3``).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) Switching features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) The driver supports the configuration of L2 forwarding rules in hardware for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) port bridging. The forwarding, broadcast and flooding domain between ports can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) be restricted through two methods: either at the L2 forwarding level (isolate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) one bridge's ports from another's) or at the VLAN port membership level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (isolate ports within the same bridge). The final forwarding decision taken by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) the hardware is a logical AND of these two sets of rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) The hardware tags all traffic internally with a port-based VLAN (pvid), or it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) decodes the VLAN information from the 802.1Q tag. Advanced VLAN classification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) is not possible. Once attributed a VLAN tag, frames are checked against the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) port's membership rules and dropped at ingress if they don't match any VLAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) This behavior is available when switch ports are enslaved to a bridge with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ``vlan_filtering 1``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) Normally the hardware is not configurable with respect to VLAN awareness, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) by changing what TPID the switch searches 802.1Q tags for, the semantics of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bridge with ``vlan_filtering 0`` can be kept (accept all traffic, tagged or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) untagged), and therefore this mode is also supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) Segregating the switch ports in multiple bridges is supported (e.g. 2 + 2), but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) all bridges should have the same level of VLAN awareness (either both have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ``vlan_filtering`` 0, or both 1). Also an inevitable limitation of the fact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) that VLAN awareness is global at the switch level is that once a bridge with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ``vlan_filtering`` enslaves at least one switch port, the other un-bridged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ports are no longer available for standalone traffic termination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) Topology and loop detection through STP is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) L2 FDB manipulation (add/delete/dump) is currently possible for the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) generation devices. Aging time of FDB entries, as well as enabling fully static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) management (no address learning and no flooding of unknown traffic) is not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) configurable in the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) A special comment about bridging with other netdevices (illustrated with an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) example):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) A board has eth0, eth1, swp0@eth1, swp1@eth1, swp2@eth1, swp3@eth1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) The switch ports (swp0-3) are under br0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) It is desired that eth0 is turned into another switched port that communicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) with swp0-3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) If br0 has vlan_filtering 0, then eth0 can simply be added to br0 with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) intended results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) If br0 has vlan_filtering 1, then a new br1 interface needs to be created that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enslaves eth0 and eth1 (the DSA master of the switch ports). This is because in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) this mode, the switch ports beneath br0 are not capable of regular traffic, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) are only used as a conduit for switchdev operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Offloads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) Time-aware scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) The switch supports a variation of the enhancements for scheduled traffic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) specified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ensure deterministic latency for priority traffic that is sent in-band with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) gate-open event in the network schedule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) This capability can be managed through the tc-taprio offload ('flags 2'). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) difference compared to the software implementation of taprio is that the latter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) would only be able to shape traffic originated from the CPU, but not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) autonomously forwarded flows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) The device has 8 traffic classes, and maps incoming frames to one of them based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) on the VLAN PCP bits (if no VLAN is present, the port-based default is used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) As described in the previous sections, depending on the value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ``vlan_filtering``, the EtherType recognized by the switch as being VLAN can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) either be the typical 0x8100 or a custom value used internally by the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for tagging. Therefore, the switch ignores the VLAN PCP if used in standalone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) or bridge mode with ``vlan_filtering=0``, as it will not recognize the 0x8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) EtherType. In these modes, injecting into a particular TX queue can only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) done by the DSA net devices, which populate the PCP field of the tagging header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) on egress. Using ``vlan_filtering=1``, the behavior is the other way around:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) offloaded flows can be steered to TX queues based on the VLAN PCP, but the DSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) net devices are no longer able to do that. To inject frames into a hardware TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) queue with VLAN awareness active, it is necessary to create a VLAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) sub-interface on the DSA master port, and send normal (0x8100) VLAN-tagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) towards the switch, with the VLAN PCP bits set appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) Management traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) notable exception: the switch always treats it with a fixed priority and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) disregards any VLAN PCP bits even if present. The traffic class for management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) traffic has a value of 7 (highest priority) at the moment, which is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) configurable in the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) Below is an example of configuring a 500 us cyclic schedule on egress port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ``swp5``. The traffic class gate for management traffic (7) is open for 100 us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) and the gates for all other traffic classes are open for 400 us::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #!/bin/bash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) set -e -u -o pipefail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) NSEC_PER_SEC="1000000000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) gatemask() {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) local tc_list="$1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) local mask=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for tc in ${tc_list}; do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mask=$((${mask} | (1 << ${tc})))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) printf "%02x" ${mask}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if ! systemctl is-active --quiet ptp4l; then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) echo "Please start the ptp4l service"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) now=$(phc_ctl /dev/ptp1 get | gawk '/clock time is/ { print $5; }')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) # Phase-align the base time to the start of the next second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sec=$(echo "${now}" | gawk -F. '{ print $1; }')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) base_time="$(((${sec} + 1) * ${NSEC_PER_SEC}))"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) tc qdisc add dev swp5 parent root handle 100 taprio \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) num_tc 8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) map 0 1 2 3 5 6 7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) base-time ${base_time} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sched-entry S $(gatemask 7) 100000 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) flags 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) It is possible to apply the tc-taprio offload on multiple egress ports. There
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) are hardware restrictions related to the fact that no gate event may trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) simultaneously on two ports. The driver checks the consistency of the schedules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) against this restriction and errors out when appropriate. Schedule analysis is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) needed to avoid this, which is outside the scope of the document.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) Routing actions (redirect, trap, drop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) The switch is able to offload flow-based redirection of packets to a set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) destination ports specified by the user. Internally, this is implemented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) making use of Virtual Links, a TTEthernet concept.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) The driver supports 2 types of keys for Virtual Links:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) - VLAN-aware virtual links: these match on destination MAC address, VLAN ID and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) VLAN PCP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) - VLAN-unaware virtual links: these match on destination MAC address only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) The VLAN awareness state of the bridge (vlan_filtering) cannot be changed while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) there are virtual link rules installed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) Composing multiple actions inside the same rule is supported. When only routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) actions are requested, the driver creates a "non-critical" virtual link. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) the action list also contains tc-gate (more details below), the virtual link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) becomes "time-critical" (draws frame buffers from a reserved memory partition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) etc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) The 3 routing actions that are supported are "trap", "drop" and "redirect".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) Example 1: send frames received on swp2 with a DA of 42:be:24:9b:76:20 to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CPU and to swp3. This type of key (DA only) when the port's VLAN awareness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) state is off::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tc qdisc add dev swp2 clsact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tc filter add dev swp2 ingress flower skip_sw dst_mac 42:be:24:9b:76:20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) action mirred egress redirect dev swp3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) action trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) Example 2: drop frames received on swp2 with a DA of 42:be:24:9b:76:20, a VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) of 100 and a PCP of 0::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tc filter add dev swp2 ingress protocol 802.1Q flower skip_sw \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) Time-based ingress policing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) The TTEthernet hardware abilities of the switch can be constrained to act
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) similarly to the Per-Stream Filtering and Policing (PSFP) clause specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) IEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tight timing-based admission control for up to 1024 flows (identified by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tuple composed of destination MAC address, VLAN ID and VLAN PCP). Packets which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) are received outside their expected reception window are dropped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) This capability can be managed through the offload of the tc-gate action. As
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) routing actions are intrinsic to virtual links in TTEthernet (which performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) explicit routing of time-critical traffic and does not leave that in the hands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) of the FDB, flooding etc), the tc-gate action may never appear alone when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) asking sja1105 to offload it. One (or more) redirect or trap actions must also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) follow along.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) Example: create a tc-taprio schedule that is phase-aligned with a tc-gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) schedule (the clocks must be synchronized by a 1588 application stack, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) outside the scope of this document). No packet delivered by the sender will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dropped. Note that the reception window is larger than the transmission window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (and much more so, in this example) to compensate for the packet propagation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) delay of the link (which can be determined by the 1588 application stack).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) Receiver (sja1105)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tc qdisc add dev swp2 clsact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) now=$(phc_ctl /dev/ptp1 get | awk '/clock time is/ {print $5}') && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) sec=$(echo $now | awk -F. '{print $1}') && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) base_time="$(((sec + 2) * 1000000000))" && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) echo "base time ${base_time}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tc filter add dev swp2 ingress flower skip_sw \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dst_mac 42:be:24:9b:76:20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) action gate base-time ${base_time} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sched-entry OPEN 60000 -1 -1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sched-entry CLOSE 40000 -1 -1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) action trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) Sender::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) now=$(phc_ctl /dev/ptp0 get | awk '/clock time is/ {print $5}') && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sec=$(echo $now | awk -F. '{print $1}') && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) base_time="$(((sec + 2) * 1000000000))" && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) echo "base time ${base_time}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tc qdisc add dev eno0 parent root taprio \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) num_tc 8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) map 0 1 2 3 4 5 6 7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) base-time ${base_time} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sched-entry S 01 50000 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sched-entry S 00 50000 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) flags 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) The engine used to schedule the ingress gate operations is the same that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) one used for the tc-taprio offload. Therefore, the restrictions regarding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) the same time (during the same 200 ns slot) still apply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) To come in handy, it is possible to share time-triggered virtual links across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) more than 1 ingress port, via flow blocks. In this case, the restriction of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) firing at the same time does not apply because there is a single schedule in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) the system, that of the shared virtual link::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tc qdisc add dev swp2 ingress_block 1 clsact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tc qdisc add dev swp3 ingress_block 1 clsact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tc filter add block 1 flower skip_sw dst_mac 42:be:24:9b:76:20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) action gate index 2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) base-time 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sched-entry OPEN 50000000 -1 -1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sched-entry CLOSE 50000000 -1 -1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) action trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) Hardware statistics for each flow are also available ("pkts" counts the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) of dropped frames, which is a sum of frames dropped due to timing violations,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) lack of destination ports and MTU enforcement checks). Byte-level counters are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) Device Tree bindings and board design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) This section references ``Documentation/devicetree/bindings/net/dsa/sja1105.txt``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) and aims to showcase some potential switch caveats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RMII PHY role and out-of-band signaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ---------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) an external oscillator (but not by the PHY).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) But the spec is rather loose and devices go outside it in several ways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) Some PHYs go against the spec and may provide an output pin where they source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) the 50 MHz clock themselves, in an attempt to be helpful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) On the other hand, the SJA1105 is only binary configurable - when in the RMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MAC role it will also attempt to drive the clock signal. To prevent this from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) happening it must be put in RMII PHY role.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) But doing so has some unintended consequences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) These are practically some extra code words (/J/ and /K/) sent prior to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) preamble of each frame. The MAC does not have this out-of-band signaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mechanism defined by the RMII spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) emulates a PHY interface fully and generates the /J/ and /K/ symbols prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) frame preambles, which the real PHY is not expected to understand. So the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) simply encodes the extra symbols received from the SJA1105-as-PHY onto the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 100Base-Tx wire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) On the other side of the wire, some link partners might discard these extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) symbols, while others might choke on them and discard the entire Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) frames that follow along. This looks like packet loss with some link partners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) but not with others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) The take-away is that in RMII mode, the SJA1105 must be let to drive the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) reference clock if connected to a PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RGMII fixed-link and internal delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) As mentioned in the bindings document, the second generation of devices has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) tunable delay lines as part of the MAC, which can be used to establish the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) correct RGMII timing budget.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) When powered up, these can shift the Rx and Tx clocks with a phase difference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) between 73.8 and 101.7 degrees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) The catch is that the delay lines need to lock onto a clock signal with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) stable frequency. This means that there must be at least 2 microseconds of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) silence between the clock at the old vs at the new frequency. Otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) lock is lost and the delay lines must be reset (powered down and back up).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) AN process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) In the situation where the switch port is connected through an RGMII fixed-link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) to a link partner whose link state life cycle is outside the control of Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (such as a different SoC), then the delay lines would remain unlocked (and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) inactive) until there is manual intervention (ifdown/ifup on the switch port).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) The take-away is that in RGMII mode, the switch's internal delays are only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) reliable if the link partner never changes link speeds, or if it does, it does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) so in a way that is coordinated with the switch port (practically, both ends of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) the fixed-link are under control of the same Linux system).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) As to why would a fixed-link interface ever change link speeds: there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) Ethernet controllers out there which come out of reset in 100 Mbps mode, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) their driver inevitably needs to change the speed and clock frequency if it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) required to work at gigabit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MDIO bus and PHY management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) The SJA1105 does not have an MDIO bus and does not perform in-band AN either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) Therefore there is no link state notification coming from the switch device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) A board would need to hook up the PHYs connected to the switch to any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MDIO bus available to Linux within the system (e.g. to the DSA master's MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) bus). Link state management then works by the driver manually keeping in sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) (over SPI commands) the MAC link speed with the settings negotiated by the PHY.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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