^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Kernel driver eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Supported chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Any EEPROM chip in the designated address range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Prefix: 'eeprom'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Addresses scanned: I2C 0x50 - 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Datasheets: Publicly available from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Atmel (www.atmel.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Catalyst (www.catsemi.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Fairchild (www.fairchildsemi.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Microchip (www.microchip.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Philips (www.semiconductor.philips.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Rohm (www.rohm.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ST (www.st.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Xicor (www.xicor.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ========= ============= ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Chip Size (bits) Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ========= ============= ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 24C01 1K 0x50 (shadows at 0x51 - 0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 24C01A 1K 0x50 - 0x57 (Typical device on DIMMs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 24C02 2K 0x50 - 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 24C04 4K 0x50, 0x52, 0x54, 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (additional data at 0x51, 0x53, 0x55, 0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 24C08 8K 0x50, 0x54 (additional data at 0x51, 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 0x53, 0x55, 0x56, 0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 24C16 16K 0x50 (additional data at 0x51 - 0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Sony 2K 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ST M34C02 2K 0x50 - 0x57, SW write protect at 0x30-37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ========= ============= ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - Frodo Looijaard <frodol@dds.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - Philip Edelbrock <phil@netroedge.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - Jean Delvare <jdelvare@suse.de>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - Greg Kroah-Hartman <greg@kroah.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) This is a simple EEPROM module meant to enable reading the first 256 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) of an EEPROM (on a SDRAM DIMM for example). However, it will access serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) EEPROMs on any I2C adapter. The supported devices are generically called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 24Cxx, and are listed above; however the numbering for these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) industry-standard devices may vary by manufacturer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) This module was a programming exercise to get used to the new project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) organization laid out by Frodo, but it should be at least completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) effective for decoding the contents of EEPROMs on DIMMs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DIMMS will typically contain a 24C01A or 24C02, or the 34C02 variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) The other devices will not be found on a DIMM because they respond to more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) than one address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DDC Monitors may contain any device. Often a 24C01, which responds to all 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) addresses, is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Recent Sony Vaio laptops have an EEPROM at 0x57. We couldn't get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) specification, so it is guess work and far from being complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) The Microchip 24AA52/24LCS52, ST M34C02, and others support an additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) software write protect register at 0x30 - 0x37 (0x20 less than the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) location). The chip responds to "write quick" detection at this address but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) does not respond to byte reads. If this register is present, the lower 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bytes of the memory array are not write protected. Any byte data write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) this address will write protect the memory array permanently, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) device will no longer respond at the 0x30-37 address. The eeprom driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) does not support this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Lacking functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Full support for larger devices (24C04, 24C08, 24C16). These are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) typically found on a PC. These devices will appear as separate devices at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) multiple addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Support for really large devices (24C32, 24C64, 24C128, 24C256, 24C512).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) These devices require two-byte address fields and are not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Enable Writing. Again, no technical reason why not, but making it easy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) to change the contents of the EEPROMs (on DIMMs anyway) also makes it easy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) to disable the DIMMs (potentially preventing the computer from booting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) until the values are restored somehow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) After inserting the module (and any other required SMBus/i2c modules), you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) should have some EEPROM directories in ``/sys/bus/i2c/devices/*`` of names such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) as "0-0050". Inside each of these is a series of files, the eeprom file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) contains the binary data from EEPROM.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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