^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ===============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Ingenic JZ47xx SoCs Timer/Counter Unit hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ===============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) hardware block. It features up to eight channels, that can be used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) counters, timers, or PWM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) have eight channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - JZ4725B introduced a separate channel, called Operating System Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 64-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - Each one of the TCU channels has its own clock, which can be reparented to three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - The watchdog and OST hardware blocks also feature a TCSR register with the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) format in their register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) OST clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - Each TCU channel works in one of two modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - mode TCU1: channels cannot work in sleep mode, but are easier to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) operate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - mode TCU2: channels can work in sleep mode, but the operation is a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) more complicated than with TCU1 channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - The mode of each TCU channel depends on the SoC used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) TCU1 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) others operate as TCU1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - Each channel can generate an interrupt. Some channels share an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) line, some don't, and this changes between SoC versions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) own interrupt line; channels 2-7 share the last interrupt line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) interrupt line; the OST uses the last interrupt line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) the OST uses the last interrupt line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) The functionalities of the TCU hardware are spread across multiple drivers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) =========== =====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clocks drivers/clk/ingenic/tcu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) interrupts drivers/irqchip/irq-ingenic-tcu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) timers drivers/clocksource/ingenic-timer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OST drivers/clocksource/ingenic-ost.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PWM drivers/pwm/pwm-jz4740.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) watchdog drivers/watchdog/jz4740_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) =========== =====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Because various functionalities of the TCU that belong to different drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) and frameworks can be controlled from the same registers, all of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) drivers access their registers through the same regmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) For more information regarding the devicetree bindings of the TCU drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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