Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) IRQ affinity on IA64 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 07.01.2002, Erich Focht <efocht@ess.nec.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) controlled. The behavior on IA64 platforms is slightly different from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Because of the usage of SAPIC mode and physical destination mode the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) IRQ target is one particular CPU and cannot be a mask of several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CPUs. Only the first non-zero bit is taken into account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Usage examples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) The target CPU has to be specified as a hexadecimal CPU mask. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) first non-zero bit is the selected CPU. This format has been kept for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) compatibility reasons with i386.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Set the delivery mode of interrupt 41 to fixed and route the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) interrupts to CPU #3 (logical CPU number) (2^3=0x08)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)      echo "8" >/proc/irq/41/smp_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Set the default route for IRQ number 41 to CPU 6 in lowest priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) delivery mode (redirectable)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)      echo "r 40" >/proc/irq/41/smp_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The output of the command::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)      cat /proc/irq/IRQ#/smp_affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) gives the target CPU mask for the specified interrupt vector. If the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mask is preceded by the character "r", the interrupt is redirectable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (i.e. lowest priority mode routing is used), otherwise its route is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Initialization and default behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ===================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) If the platform features IRQ redirection (info provided by SAL) all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IO-SAPIC interrupts are initialized with CPU#0 as their default target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) and the routing is the so called "lowest priority mode" (actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) fixed SAPIC mode with hint). The XTP chipset registers are used as hints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) for the IRQ routing. Currently in Linux XTP registers can have three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	- minimal for an idle task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	- normal if any other task runs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	- maximal if the CPU is going to be switched off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) The IRQ is routed to the CPU with lowest XTP register value, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) search begins at the default CPU. Therefore most of the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) will be handled by CPU #0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) If the platform doesn't feature interrupt redirection IOSAPIC fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) routing is used. The target CPUs are distributed in a round robin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) manner. IRQs will be routed only to the selected target CPUs. Check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) with::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)         cat /proc/interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Comments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) On large (multi-node) systems it is recommended to route the IRQs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) the node to which the corresponding device is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) For systems like the NEC AzusA we get IRQ node-affinity for free. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) is because usually the chipsets on each node redirect the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) only to their own CPUs (as they cannot see the XTP registers on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) other nodes).