^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) The SMBus Protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) The following is a summary of the SMBus protocol. It applies to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) all revisions of the protocol (1.0, 1.1, and 2.0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Certain protocol features which are not supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) this package are briefly described at the end of this document.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Some adapters understand only the SMBus (System Management Bus) protocol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) which is a subset from the I2C protocol. Fortunately, many devices use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) only the same subset, which makes it possible to put them on an SMBus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) If you write a driver for some I2C device, please try to use the SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) commands if at all possible (if the device uses only that subset of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) I2C protocol). This makes it possible to use the device driver on both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) SMBus adapters and I2C adapters (the SMBus command set is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) translated to I2C on I2C adapters, but plain I2C commands can not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) handled at all on most pure SMBus adapters).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Below is a list of SMBus protocol operations, and the functions executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) them. Note that the names used in the SMBus protocol specifications usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) don't match these function names. For some of the operations which pass a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) single data byte, the functions using SMBus protocol operation names execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) a different protocol operation entirely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Each transaction type corresponds to a functionality flag. Before calling a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) transaction function, a device driver should always check (just once) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) the corresponding functionality flag to ensure that the underlying I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) adapter supports the transaction in question. See :doc:`functionality` for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Key to symbols
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) =============== =============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) S Start condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) P Stop condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) get a 10 bit I2C address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Comm (8 bits) Command byte, a data byte which often selects a register on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) for 16 bit data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Count (8 bits) A data byte containing the length of a block operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [..] Data sent by I2C device, as opposed to data sent by the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) =============== =============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SMBus Quick Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) This sends a single bit to the device, at the place of the Rd/Wr bit::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) S Addr Rd/Wr [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Functionality flag: I2C_FUNC_SMBUS_QUICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SMBus Receive Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Implemented by i2c_smbus_read_byte()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) This reads a single byte from a device, without specifying a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) register. Some devices are so simple that this interface is enough; for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) others, it is a shorthand if you want to read the same register as in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) the previous SMBus command::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) S Addr Rd [A] [Data] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Functionality flag: I2C_FUNC_SMBUS_READ_BYTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SMBus Send Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Implemented by i2c_smbus_write_byte()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) This operation is the reverse of Receive Byte: it sends a single byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) to a device. See Receive Byte for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) S Addr Wr [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Functionality flag: I2C_FUNC_SMBUS_WRITE_BYTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SMBus Read Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Implemented by i2c_smbus_read_byte_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) This reads a single byte from a device, from a designated register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) The register is specified through the Comm byte::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Functionality flag: I2C_FUNC_SMBUS_READ_BYTE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SMBus Read Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Implemented by i2c_smbus_read_word_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) This operation is very like Read Byte; again, data is read from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) device, from a designated register that is specified through the Comm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) byte. But this time, the data is a complete word (16 bits)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) Functionality flag: I2C_FUNC_SMBUS_READ_WORD_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) Note the convenience function i2c_smbus_read_word_swapped() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) available for reads where the two data bytes are the other way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) around (not SMBus compliant, but very popular.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SMBus Write Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Implemented by i2c_smbus_write_byte_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) This writes a single byte to a device, to a designated register. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) register is specified through the Comm byte. This is the opposite of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) the Read Byte operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) S Addr Wr [A] Comm [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) Functionality flag: I2C_FUNC_SMBUS_WRITE_BYTE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SMBus Write Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) Implemented by i2c_smbus_write_word_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) This is the opposite of the Read Word operation. 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) of data are written to a device, to the designated register that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) specified through the Comm byte::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Functionality flag: I2C_FUNC_SMBUS_WRITE_WORD_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) Note the convenience function i2c_smbus_write_word_swapped() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) available for writes where the two data bytes are the other way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) around (not SMBus compliant, but very popular.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SMBus Process Call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) This command selects a device register (through the Comm byte), sends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 16 bits of data to it, and reads 16 bits of data in return::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) S Addr Rd [A] [DataLow] A [DataHigh] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Functionality flag: I2C_FUNC_SMBUS_PROC_CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SMBus Block Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) Implemented by i2c_smbus_read_block_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) This command reads a block of up to 32 bytes from a device, from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) designated register that is specified through the Comm byte. The amount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) of data is specified by the device in the Count byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) S Addr Wr [A] Comm [A]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) Functionality flag: I2C_FUNC_SMBUS_READ_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SMBus Block Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) Implemented by i2c_smbus_write_block_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) The opposite of the Block Read command, this writes up to 32 bytes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) a device, to a designated register that is specified through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) Comm byte. The amount of data is specified in the Count byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) Functionality flag: I2C_FUNC_SMBUS_WRITE_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SMBus Block Write - Block Read Process Call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SMBus Block Write - Block Read Process Call was introduced in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) Revision 2.0 of the specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) This command selects a device register (through the Comm byte), sends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) S Addr Wr [A] Comm [A] Count [A] Data [A] ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) S Addr Rd [A] [Count] A [Data] ... A P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) Functionality flag: I2C_FUNC_SMBUS_BLOCK_PROC_CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SMBus Host Notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) This command is sent from a SMBus device acting as a master to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SMBus host acting as a slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) It is the same form as Write Word, with the command code replaced by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) alerting device's address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) This is implemented in the following way in the Linux kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * I2C bus drivers which support SMBus Host Notify should report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) I2C_FUNC_SMBUS_HOST_NOTIFY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * I2C bus drivers trigger SMBus Host Notify by a call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) i2c_handle_smbus_host_notify().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * I2C drivers for devices which can trigger SMBus Host Notify will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) client->irq assigned to a Host Notify IRQ if noone else specified an other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) There is currently no way to retrieve the data parameter from the client.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) Packet Error Checking (PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ===========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) Packet Error Checking was introduced in Revision 1.1 of the specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PEC adds a CRC-8 error-checking byte to transfers using it, immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) before the terminating STOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) Address Resolution Protocol (ARP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) The Address Resolution Protocol was introduced in Revision 2.0 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) the specification. It is a higher-layer protocol which uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) messages above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ARP adds device enumeration and dynamic address assignment to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) the protocol. All ARP communications use slave address 0x61 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) require PEC checksums.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SMBus Alert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SMBus Alert was introduced in Revision 1.0 of the specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) The SMBus alert protocol allows several SMBus slave devices to share a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) single interrupt pin on the SMBus master, while still allowing the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) to know which slave triggered the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) This is implemented the following way in the Linux kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * I2C bus drivers which support SMBus alert should call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) i2c_new_smbus_alert_device() to install SMBus alert support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * I2C drivers for devices which can trigger SMBus alerts should implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) the optional alert() callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) I2C Block Transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) The following I2C block transactions are similar to the SMBus Block Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) and Write operations, except these do not have a Count byte. They are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) supported by the SMBus layer and are described here for completeness, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) they are *NOT* defined by the SMBus specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) I2C block transactions do not limit the number of bytes transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) but the SMBus layer places a limit of 32 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) I2C Block Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) Implemented by i2c_smbus_read_i2c_block_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) This command reads a block of bytes from a device, from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) designated register that is specified through the Comm byte::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) S Addr Wr [A] Comm [A]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) Functionality flag: I2C_FUNC_SMBUS_READ_I2C_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) I2C Block Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) Implemented by i2c_smbus_write_i2c_block_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) The opposite of the Block Read command, this writes bytes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) a device, to a designated register that is specified through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) Comm byte. Note that command lengths of 0, 2, or more bytes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) supported as they are indistinguishable from data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) Functionality flag: I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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