^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Linux I2C slave interface description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) by Wolfram Sang <wsa@sang-engineering.com> in 2014-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Linux can also be an I2C slave if the I2C controller in use has slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) functionality. For that to work, one needs slave support in the bus driver plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) a hardware independent software backend providing the actual functionality. An
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) example for the latter is the slave-eeprom driver, which acts as a dual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) driver. While another I2C master on the bus can access it like a regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) EEPROM, the Linux I2C slave can access the content via sysfs and handle data as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) needed. The backend driver and the I2C bus driver communicate via events. Here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) is a small graph visualizing the data flow and the means by which data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) transported. The dotted line marks only one example. The backend could also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) use a character device, be in-kernel only, or something completely different::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) e.g. sysfs I2C slave events I/O registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) +-----------+ v +---------+ v +--------+ v +------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) | Userspace +........+ Backend +-----------+ Driver +-----+ Controller |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) +-----------+ +---------+ +--------+ +------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ----------------------------------------------------------------+-- I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) --------------------------------------------------------------+---- Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Note: Technically, there is also the I2C core between the backend and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) driver. However, at this time of writing, the layer is transparent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) User manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) I2C slave backends behave like standard I2C clients. So, you can instantiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) them as described in the document 'instantiating-devices'. The only difference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) is that i2c slave backends have their own address space. So, you have to add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0x1000 to the address you would originally request. An example for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) instantiating the slave-eeprom driver from userspace at the 7 bit address 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) on bus 1::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Each backend should come with separate documentation to describe its specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) behaviour and setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Developer manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) First, the events which are used by the bus driver and the backend will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) described in detail. After that, some implementation hints for extending bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) drivers and writing backends will be given.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) I2C slave events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) The bus driver sends an event to the backend using the following function::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = i2c_slave_event(client, event, &val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 'client' describes the I2C slave device. 'event' is one of the special event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) types described hereafter. 'val' holds an u8 value for the data byte to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) read/written and is thus bidirectional. The pointer to val must always be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) provided even if val is not used for an event, i.e. don't use NULL here. 'ret'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) is the return value from the backend. Mandatory events must be provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bus drivers and must be checked for by backend drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Event types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * I2C_SLAVE_WRITE_REQUESTED (mandatory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 'val': unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 'ret': always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Another I2C master wants to write data to us. This event should be sent once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) our own address and the write bit was detected. The data did not arrive yet, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) there is nothing to process or return. Wakeup or initialization probably needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) to be done, though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * I2C_SLAVE_READ_REQUESTED (mandatory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 'val': backend returns first byte to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 'ret': always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Another I2C master wants to read data from us. This event should be sent once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) our own address and the read bit was detected. After returning, the bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) should transmit the first byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * I2C_SLAVE_WRITE_RECEIVED (mandatory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 'val': bus driver delivers received byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 'ret': 0 if the byte should be acked, some errno if the byte should be nacked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) is zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) should be nacked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * I2C_SLAVE_READ_PROCESSED (mandatory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 'val': backend returns next byte to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 'ret': always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) The bus driver requests the next byte to be sent to another I2C master in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 'val'. Important: This does not mean that the previous byte has been acked, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) only means that the previous byte is shifted out to the bus! To ensure seamless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) transmission, most hardware requests the next byte when the previous one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) still shifted out. If the master sends NACK and stops reading after the byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) currently shifted out, this byte requested here is never used. It very likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) needs to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) your backend, though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * I2C_SLAVE_STOP (mandatory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 'val': unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 'ret': always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) A stop condition was received. This can happen anytime and the backend should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reset its state machine for I2C transfers to be able to receive new requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) Software backends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) If you want to write a software backend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * use a standard i2c_driver and its matching mechanisms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * write the slave_callback which handles the above slave events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) (best using a state machine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * register this callback via i2c_slave_register()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Check the i2c-slave-eeprom driver as an example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Bus driver support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) If you want to add slave support to the bus driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * implement calls to register/unregister the slave and add those to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_algorithm. When registering, you probably need to set the I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) slave address and enable slave specific interrupts. If you use runtime pm, you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) should use pm_runtime_get_sync() because your device usually needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) powered on always to be able to detect its slave address. When unregistering,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) do the inverse of the above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Catch the slave interrupts and send appropriate i2c_slave_events to the backend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) Note that most hardware supports being master _and_ slave on the same bus. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if you extend a bus driver, please make sure that the driver supports that as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) well. In almost all cases, slave support does not need to disable the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) Check the i2c-rcar driver as an example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) About ACK/NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) It is good behaviour to always ACK the address phase, so the master knows if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) device is basically present or if it mysteriously disappeared. Using NACK to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) state being busy is troublesome. SMBus demands to always ACK the address phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) while the I2C specification is more loose on that. Most I2C controllers also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) automatically ACK when detecting their slave addresses, so there is no option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) to NACK them. For those reasons, this API does not support NACK in the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) Currently, there is no slave event to report if the master did ACK or NACK a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) byte when it reads from us. We could make this an optional event if the need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) arises. However, cases should be extremely rare because the master is expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) to send STOP after that and we have an event for that. Also, keep in mind not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) all I2C controllers have the possibility to report that event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) About buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) During development of this API, the question of using buffers instead of just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bytes came up. Such an extension might be possible, usefulness is unclear at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) this time of writing. Some points to keep in mind when using buffers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Buffers should be opt-in and backend drivers will always have to support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) byte-based transactions as the ultimate fallback anyhow because this is how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) the majority of HW works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * For backends simulating hardware registers, buffers are largely not helpful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) because after each byte written an action should be immediately triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) For reads, the data kept in the buffer might get stale if the backend just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) updated a register because of internal processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * A master can send STOP at any time. For partially transferred buffers, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) means additional code to handle this exception. Such code tends to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) error-prone.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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