^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) The I2C Protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) This document describes the I2C protocol. Or will, when it is finished :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Key to symbols
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) =============== =============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) S Start condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) P Stop condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) get a 10 bit I2C address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Comm (8 bits) Command byte, a data byte which often selects a register on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) for 16 bit data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Count (8 bits) A data byte containing the length of a block operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [..] Data sent by I2C device, as opposed to data sent by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) host adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) =============== =============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Simple send transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Implemented by i2c_master_send()::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Simple receive transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ==========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Implemented by i2c_master_recv()::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Combined transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Implemented by i2c_transfer().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) They are just like the above transactions, but instead of a stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) condition P a start condition S is sent and the transaction continues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) An example of a byte read, followed by a byte write::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Modified transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) The following modifications to the I2C protocol can also be generated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) setting these flags for I2C messages. With the exception of I2C_M_NOSTART, they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) are usually only needed to work around device issues:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) I2C_M_IGNORE_NAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Normally message is interrupted immediately if there is [NA] from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) client. Setting this flag treats any [NA] as [A], and all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) message is sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) These messages may still fail to SCL lo->hi timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) I2C_M_NO_RD_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) In a read message, master A/NA bit is skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) I2C_M_NOSTART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) point. For example, setting I2C_M_NOSTART on the second partial message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) generates something like::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) S Addr Rd [A] [Data] NA Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) If you set the I2C_M_NOSTART variable for the first partial message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) we do not generate Addr, but we do generate the start condition S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) This will probably confuse all other clients on your bus, so don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) try this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) This is often used to gather transmits from multiple data buffers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) system memory into something that appears as a single transfer to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) I2C device but may also be used between direction changes by some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rare devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) I2C_M_REV_DIR_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) This toggles the Rd/Wr flag. That is, if you want to do a write, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) need to emit an Rd instead of a Wr, or vice versa, you set this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) flag. For example::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) I2C_M_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Force a stop condition (P) after the message. Some I2C related protocols
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) like SCCB require that. Normally, you really don't want to get interrupted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) between the messages of one transfer.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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