Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) Driver i2c-mlxcpld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Author: Michael Shych <michaelsh@mellanox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) This is the Mellanox I2C controller logic, implemented in Lattice CPLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Device supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - Master mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - One physical bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - Polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) This controller is equipped within the next Mellanox systems:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "msn2740", "msn2100".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The next transaction types are supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  - Receive Byte/Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  - Send Byte/Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  - Read Byte/Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  - Write Byte/Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) =============== === =======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) CPBLTY		0x0 - capability reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			Bits [6:5] - transaction length. b01 - 72B is supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			36B in other case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			Bit 7 - SMBus block read support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CTRL		0x1 - control reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			Resets all the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) HALF_CYC	0x4 - cycle reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			units).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) I2C_HOLD	0x5 - hold reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			OE (output enable) is delayed by value set to this register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			(in LPC_CLK units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CMD			0x6 - command reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			Bit 0, 0 = write, 1 = read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			Bits [7:1] - the 7bit Address of the I2C device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			It should be written last as it triggers an I2C transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NUM_DATA	0x7 - data size reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			Number of data bytes to write in read transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) NUM_ADDR	0x8 - address reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			Number of address bytes to write in read transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) STATUS		0x9 - status reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			Bit 0 - transaction is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			Bit 4 - ACK/NACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DATAx		0xa - 0x54  - 68 bytes data buffer regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			For write transaction address is specified in four first bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			(DATA1 - DATA4), data starting from DATA4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			For read transactions address is sent in a separate transaction and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			specified in the four first bytes (DATA0 - DATA3). Data is read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			starting from DATA0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) =============== === =======================================================================