Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) Kernel driver i2c-ismt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Supported adapters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   * Intel S12xx series SOCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	Bill Brown <bill.e.brown@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Module Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * bus_speed (unsigned int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Allows changing of the bus speed.  Normally, the bus speed is set by the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) and never needs to be changed.  However, some SMBus analyzers are too slow for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) monitoring the bus during debug, thus the need for this module parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Specify the bus speed in kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Available bus frequency settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   ====   =========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   0      no change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   80     kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   100    kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   400    kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   1000   kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   ====   =========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The S12xx series of SOCs have a pair of integrated SMBus 2.0 controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) targeted primarily at the microserver and storage markets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) The S12xx series contain a pair of PCI functions.  An output of lspci will show
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) something similar to the following::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   00:13.0 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   00:13.1 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 1