^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Kernel driver vt1211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Supported chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * VIA VT1211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Prefix: 'vt1211'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Addresses scanned: none, address read from Super-I/O config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Datasheet: Provided by VIA upon request and under NDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Authors: Juerg Haefliger <juergh@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) This driver is based on the driver for kernel 2.4 by Mark D. Studebaker and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) its port to kernel 2.6 by Lars Ekman.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Thanks to Joseph Chan and Fiona Gatt from VIA for providing documentation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) technical support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Module Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * uch_config: int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Override the BIOS default universal channel (UCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) configuration for channels 1-5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Legal values are in the range of 0-31. Bit 0 maps to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enables the thermal input of that particular UCH and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) setting a bit to 0 enables the voltage input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * int_mode: int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Override the BIOS default temperature interrupt mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The only possible value is 0 which forces interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mode 0. In this mode, any pending interrupt is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) when the status register is read but is regenerated as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) long as the temperature stays above the hysteresis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Be aware that overriding BIOS defaults might cause some unwanted side effects!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) The VIA VT1211 Super-I/O chip includes complete hardware monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) capabilities. It monitors 2 dedicated temperature sensor inputs (temp1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) temp2), 1 dedicated voltage (in5) and 2 fans. Additionally, the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) implements 5 universal input channels (UCH1-5) that can be individually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) programmed to either monitor a voltage or a temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) This chip also provides manual and automatic control of fan speeds (according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) to the datasheet). The driver only supports automatic control since the manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mode doesn't seem to work as advertised in the datasheet. In fact I couldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) get manual mode to work at all! Be aware that automatic mode hasn't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tested very well (due to the fact that my EPIA M10000 doesn't have the fans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) connected to the PWM outputs of the VT1211 :-().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) The following table shows the relationship between the vt1211 inputs and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sysfs nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) =============== ============== =========== ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Sensor Voltage Mode Temp Mode Default Use (from the datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) =============== ============== =========== ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Reading 1 temp1 Intel thermal diode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Reading 3 temp2 Internal thermal diode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) UCH1/Reading2 in0 temp3 NTC type thermistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) UCH2 in1 temp4 +2.5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) UCH3 in2 temp5 VccP (processor core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) UCH4 in3 temp6 +5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) UCH5 in4 temp7 +12V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) +3.3V in5 Internal VCC (+3.3V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) =============== ============== =========== ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Voltage Monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) range is thus from 0 to 2.60V. Voltage values outside of this range need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) external scaling resistors. This external scaling needs to be compensated for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) via compute lines in sensors.conf, like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) compute inx @*(1+R1/R2), @/(1+R1/R2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) The board level scaling resistors according to VIA's recommendation are as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) follows. And this is of course totally dependent on the actual board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) implementation :-) You will have to find documentation for your own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) motherboard and edit sensors.conf accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ============= ====== ====== ========= ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Voltage R1 R2 Divider Raw Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ============= ====== ====== ========= ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) +2.5V 2K 10K 1.2 2083 mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) VccP --- --- 1.0 1400 mV [1]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) +5V 14K 10K 2.4 2083 mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) +12V 47K 10K 5.7 2105 mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) +3.3V (int) 2K 3.4K 1.588 3300 mV [2]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) +3.3V (ext) 6.8K 10K 1.68 1964 mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ============= ====== ====== ========= ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .. [1] Depending on the CPU (1.4V is for a VIA C3 Nehemiah).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .. [2] R1 and R2 for 3.3V (int) are internal to the VT1211 chip and the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) performs the scaling and returns the properly scaled voltage value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Each measured voltage has an associated low and high limit which triggers an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) alarm when crossed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Temperature Monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Temperatures are reported in millidegree Celsius. Each measured temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) has a high limit which triggers an alarm if crossed. There is an associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hysteresis value with each temperature below which the temperature has to drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) before the alarm is cleared (this is only true for interrupt mode 0). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) interrupt mode can be forced to 0 in case the BIOS doesn't do it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) automatically. See the 'Module Parameters' section for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) All temperature channels except temp2 are external. Temp2 is the VT1211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) internal thermal diode and the driver does all the scaling for temp2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) returns the temperature in millidegree Celsius. For the external channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) temp1 and temp3-temp7, scaling depends on the board implementation and needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) to be performed in userspace via sensors.conf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Temp1 is an Intel-type thermal diode which requires the following formula to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) convert between sysfs readings and real temperatures:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) compute temp1 (@-Offset)/Gain, (@*Gain)+Offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) According to the VIA VT1211 BIOS porting guide, the following gain and offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) values should be used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) =============== ======== ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Diode Type Offset Gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) =============== ======== ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) Intel CPU 88.638 0.9528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 65.000 0.9686 [3]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) VIA C3 Ezra 83.869 0.9528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) VIA C3 Ezra-T 73.869 0.9528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) =============== ======== ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .. [3] This is the formula from the lm_sensors 2.10.0 sensors.conf file. I don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) know where it comes from or how it was derived, it's just listed here for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) completeness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) Temp3-temp7 support NTC thermistors. For these channels, the driver returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) the voltages as seen at the individual pins of UCH1-UCH5. The voltage at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pin (Vpin) is formed by a voltage divider made of the thermistor (Rth) and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) scaling resistor (Rs)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) Vpin = 2200 * Rth / (Rs + Rth) (2200 is the ADC max limit of 2200 mV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) The equation for the thermistor is as follows (google it if you want to know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) more about it)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) Rth = Ro * exp(B * (1 / T - 1 / To)) (To is 298.15K (25C) and Ro is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) nominal resistance at 25C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) Mingling the above two equations and assuming Rs = Ro and B = 3435 yields the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) following formula for sensors.conf::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) compute tempx 1 / (1 / 298.15 - (` (2200 / @ - 1)) / 3435) - 273.15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 2200 / (1 + (^ (3435 / 298.15 - 3435 / (273.15 + @))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) Fan Speed Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) The VT1211 provides 2 programmable PWM outputs to control the speeds of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fans. Writing a 2 to any of the two pwm[1-2]_enable sysfs nodes will put the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PWM controller in automatic mode. There is only a single controller that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) controls both PWM outputs but each PWM output can be individually enabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) Each PWM has 4 associated distinct output duty-cycles: full, high, low and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) off. Full and off are internally hard-wired to 255 (100%) and 0 (0%),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) respectively. High and low can be programmed via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pwm[1-2]_auto_point[2-3]_pwm. Each PWM output can be associated with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) different thermal input but - and here's the weird part - only one set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) thermal thresholds exist that controls both PWMs output duty-cycles. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) thermal thresholds are accessible via pwm[1-2]_auto_point[1-4]_temp. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) that even though there are 2 sets of 4 auto points each, they map to the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) registers in the VT1211 and programming one set is sufficient (actually only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) the first set pwm1_auto_point[1-4]_temp is writable, the second set is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) read-only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ========================== =========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PWM Auto Point PWM Output Duty-Cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ========================== =========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pwm[1-2]_auto_point3_pwm high speed duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pwm[1-2]_auto_point2_pwm low speed duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ========================== =========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ========================== =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) Temp Auto Point Thermal Threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ========================== =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pwm[1-2]_auto_point4_temp full speed temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pwm[1-2]_auto_point3_temp high speed temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pwm[1-2]_auto_point2_temp low speed temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pwm[1-2]_auto_point1_temp off temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ========================== =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) Long story short, the controller implements the following algorithm to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PWM output duty-cycle based on the input temperature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) =================== ======================= ========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) Thermal Threshold Output Duty-Cycle Output Duty-Cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (Rising Temp) (Falling Temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) =================== ======================= ========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) - full speed duty-cycle full speed duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) full speed temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) - high speed duty-cycle full speed duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) high speed temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) - low speed duty-cycle high speed duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) low speed temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) - off duty-cycle low speed duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) off temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) =================== ======================= ========================
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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