^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Kernel driver smsc47b397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Supported chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * SMSC LPC47B397-NC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * SMSC SCH5307-NS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * SMSC SCH5317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Prefix: 'smsc47b397'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Addresses scanned: none, address read from Super I/O config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Datasheet: In this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - Mark M. Hoffman <mhoffman@lightlink.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - Utilitek Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) November 23, 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) The following specification describes the SMSC LPC47B397-NC [1]_ sensor chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) (for which there is no public datasheet available). This document was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) provided by Craig Kelly (In-Store Broadcast Network) and edited/corrected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) by Mark M. Hoffman <mhoffman@lightlink.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .. [1] And SMSC SCH5307-NS and SCH5317, which have different device IDs but are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) otherwise compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) -------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Methods for detecting the HP SIO and reading the thermal data on a dc7100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) -------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) The thermal information on the dc7100 is contained in the SIO Hardware Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (HWM). The information is accessed through an index/data pair. The index/data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x480 and 0x481 for the index/data pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Reading temperature information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) The temperature information is located in the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) =============== ======= =======================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Temp1 0x25 (Currently, this reflects the CPU temp on all systems).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Temp2 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Temp3 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Temp4 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) =============== ======= =======================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Programming Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) The following is an example of how to read the HWM temperature registers::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MOV DX,480H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MOV AX,25H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OUT DX,AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MOV DX,481H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) IN AL,DX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) AL contains the data in hex, the temperature in Celsius is the decimal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) equivalent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Ex: If AL contains 0x2A, the temperature is 42 degrees C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Reading tach information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) The fan speed information is located in the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) =============== ======= ======= =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) LSB MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Tach1 0x28 0x29 (Currently, this reflects the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) fan speed on all systems).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Tach2 0x2A 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Tach3 0x2C 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Tach4 0x2E 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) =============== ======= ======= =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .. Important::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Reading the tach LSB locks the tach MSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) The LSB Must be read first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) How to convert the tach reading to RPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) The tach reading (TCount) is given by: (Tach MSB * 256) + (Tach LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) The SIO counts the number of 90kHz (11.111us) pulses per revolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RPM = 60/(TCount * 11.111us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) Example::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) Reg 0x28 = 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Reg 0x29 = 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) TCount = 0x89B = 2203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RPM = 60 / (2203 * 11.11111 E-6) = 2451 RPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Obtaining the SIO version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Configuration Sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) To program the configuration registers, the following sequence must be followed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 1. Enter Configuration Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 2. Configure the Configuration Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 3. Exit Configuration Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Enter Configuration Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ^^^^^^^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) To place the chip into the Configuration State The config key (0x55) is written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) to the CONFIG PORT (0x2E).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Configuration Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) In configuration mode, the INDEX PORT is located at the CONFIG PORT address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) the DATA PORT is at INDEX PORT address + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) The desired configuration registers are accessed in two steps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) a. Write the index of the Logical Device Number Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (i.e., 0x07) to the INDEX PORT and then write the number of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) desired logical device to the DATA PORT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) b. Write the address of the desired configuration register within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) logical device to the INDEX PORT and then write or read the config-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uration register through the DATA PORT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) If accessing the Global Configuration Registers, step (a) is not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Exit Configuration Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ^^^^^^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) To exit the Configuration State the write 0xAA to the CONFIG PORT (0x2E).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) The chip returns to the RUN State. (This is important).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Programming Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ^^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) The following is an example of how to read the SIO Device ID located at 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ; ENTER CONFIGURATION MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MOV AX,055H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) OUT DX,AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ; GLOBAL CONFIGURATION REGISTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MOV AL,20H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) OUT DX,AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ; READ THE DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MOV DX,02FH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IN AL,DX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ; EXIT CONFIGURATION MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MOV AX,0AAH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) OUT DX,AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) The registers of interest for identifying the SIO on the dc7100 are Device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (0x20) and Device Rev (0x21).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) The Device ID will read 0x6F (0x81 for SCH5307-NS, and 0x85 for SCH5317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) The Device Rev currently reads 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) Obtaining the HWM Base Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) The following is an example of how to read the HWM Base Address located in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Logical Device 8::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ; ENTER CONFIGURATION MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MOV AX,055H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) OUT DX,AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ; CONFIGURE REGISTER CRE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ; LOGICAL DEVICE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MOV AL,07H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) OUT DX,AL ;Point to LD# Config Reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MOV DX,02FH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MOV AL, 08H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) OUT DX,AL;Point to Logical Device 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MOV AL,60H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) OUT DX,AL ; Point to HWM Base Addr MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MOV DX,02FH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IN AL,DX ; Get MSB of HWM Base Addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ; EXIT CONFIGURATION MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MOV DX,02EH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MOV AX,0AAH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) OUT DX,AL
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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