^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Kernel driver lm77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Supported chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * National Semiconductor LM77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Prefix: 'lm77'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Addresses scanned: I2C 0x48 - 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Datasheet: Publicly available at the National Semiconductor website
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) http://www.national.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Author: Andras BALI <drewie@freemail.hu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) The LM77 implements one temperature sensor. The temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) sensor incorporates a band-gap type temperature sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 10-bit ADC, and a digital comparator with user-programmable upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) and lower limit values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The LM77 implements 3 limits: low (temp1_min), high (temp1_max) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) critical (temp1_crit.) It also implements an hysteresis mechanism which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) applies to all 3 limits. The relative difference is stored in a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) register on the chip, which means that the relative difference between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the limit and its hysteresis is always the same for all 3 limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) This implementation detail implies the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * When setting a limit, its hysteresis will automatically follow, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) difference staying unchanged. For example, if the old critical limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) was 80 degrees C, and the hysteresis was 75 degrees C, and you change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) the critical limit to 90 degrees C, then the hysteresis will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) automatically change to 85 degrees C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * All 3 hysteresis can't be set independently. We decided to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) temp1_crit_hyst writable, while temp1_min_hyst and temp1_max_hyst are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) read-only. Setting temp1_crit_hyst writes the difference between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) temp1_crit_hyst and temp1_crit into the chip, and the same relative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) hysteresis applies automatically to the low and high limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The limits should be set before the hysteresis.