^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Kernel driver f71805f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Supported chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Fintek F71805F/FG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Prefix: 'f71805f'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Addresses scanned: none, address read from Super I/O config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Datasheet: Available from the Fintek website
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Fintek F71806F/FG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Prefix: 'f71872f'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Addresses scanned: none, address read from Super I/O config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Datasheet: Available from the Fintek website
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Fintek F71872F/FG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Prefix: 'f71872f'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Addresses scanned: none, address read from Super I/O config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Datasheet: Available from the Fintek website
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Author: Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Thanks to Denis Kieft from Barracuda Networks for the donation of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) test system (custom Jetway K8M8MS motherboard, with CPU and RAM) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) for providing initial documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Thanks to Kris Chen and Aaron Huang from Fintek for answering technical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) questions and providing additional documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Thanks to Chris Lin from Jetway for providing wiring schematics and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) answering technical questions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) capabilities. It can monitor up to 9 voltages (counting its own power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) source), 3 fans and 3 temperature sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) This chip also has fan controlling features, using either DC or PWM, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) three different modes (one manual, two automatic).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) The Fintek F71872F/FG Super I/O chip is almost the same, with two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) additional internal voltages monitored (VSB and battery). It also features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 6 VID inputs. The VID inputs are not yet supported by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) The Fintek F71806F/FG Super-I/O chip is essentially the same as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) F71872F/FG, and is undistinguishable therefrom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) The driver assumes that no more than one chip is present, which seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reasonable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Voltage Monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) range is thus from 0 to 2.040 V. Voltage values outside of this range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) need external resistors. An exception is in0, which is used to monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) the chip's own power source (+3.3V), and is divided internally by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) factor 2. For the F71872F/FG, in9 (VSB) and in10 (battery) are also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) divided internally by a factor 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) The two LSB of the voltage limit registers are not used (always 0), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) you can only set the limits in steps of 32 mV (before scaling).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) The wirings and resistor values suggested by Fintek are as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ======= ======= =========== ==== ======= ============ ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) in pin expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) name use R1 R2 divider raw val.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ======= ======= =========== ==== ======= ============ ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) in0 VCC VCC3.3V int. int. 2.00 1.65 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) in5 VIN5 +12V 200K 20K 11.00 1.05 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) in8 VIN8 VSB5V 200K 47K 1.00 0.95 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) in10 VSB VSB3.3V int. int. 2.00 1.65 V [3]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) in9 VBAT VBATTERY int. int. 2.00 1.50 V [3]_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ======= ======= =========== ==== ======= ============ ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .. [1] Depends on your hardware setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .. [2] Obviously not correct, swapping R1 and R2 would make more sense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .. [3] F71872F/FG only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) These values can be used as hints at best, as motherboard manufacturers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) are free to use a completely different setup. As a matter of fact, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Jetway K8M8MS uses a significantly different setup. You will have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) find out documentation about your own motherboard, and edit sensors.conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Each voltage measured has associated low and high limits, each of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) triggers an alarm when crossed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Fan Monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Fan rotation speeds are reported as 12-bit values from a gated clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) signal. Speeds down to 366 RPM can be measured. There is no theoretical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) high limit, but values over 6000 RPM seem to cause problem. The effective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) resolution is much lower than you would expect, the step between different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) register values being 10 rather than 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) The chip assumes 2 pulse-per-revolution fans.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) An alarm is triggered if the rotation speed drops below a programmable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) limit or is too low to be measured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Temperature Monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) Temperatures are reported in degrees Celsius. Each temperature measured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) has a high limit, those crossing triggers an alarm. There is an associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) hysteresis value, below which the temperature has to drop before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) alarm is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) All temperature channels are external, there is no embedded temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) sensor. Each channel can be used for connecting either a thermal diode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) or a thermistor. The driver reports the currently selected mode, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) doesn't allow changing it. In theory, the BIOS should have configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) everything properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Fan Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Both PWM (pulse-width modulation) and DC fan speed control methods are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) supported. The right one to use depends on external circuitry on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) motherboard, so the driver assumes that the BIOS set the method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) properly. The driver will report the method, but won't let you change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) When the PWM method is used, you can select the operating frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) from 187.5 kHz (default) to 31 Hz. The best frequency depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) fan model. As a rule of thumb, lower frequencies seem to give better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) control, but may generate annoying high-pitch noise. So a frequency just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) above the audible range, such as 25 kHz, may be a good choice; if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) doesn't give you good linear control, try reducing it. Fintek recommends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) not going below 1 kHz, as the fan tachometers get confused by lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) frequencies as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) When the DC method is used, Fintek recommends not going below 5 V, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) corresponds to a pwm value of 106 for the driver. The driver doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enforce this limit though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) Three different fan control modes are supported; the mode number is written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) to the pwm<n>_enable file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 1: Manual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) You ask for a specific PWM duty cycle or DC voltage by writing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pwm<n> file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * 2: Temperature mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) You define 3 temperature/fan speed trip points using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pwm<n>_auto_point<m>_temp and _fan files. These define a staircase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) relationship between temperature and fan speed with two additional points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) interpolated between the values that you define. When the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) is below auto_point1_temp the fan is switched off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * 3: Fan speed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) You ask for a specific fan speed by writing to the fan<n>_target file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Both of the automatic modes require that pwm1 corresponds to fan1, pwm2 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) fan2 and pwm3 to fan3. Temperature mode also requires that temp1 corresponds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) to pwm1 and fan1, etc.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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