^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Kernel driver emc1403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Supported chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * SMSC / Microchip EMC1402, EMC1412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Addresses scanned: I2C 0x18, 0x1c, 0x29, 0x4c, 0x4d, 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Prefix: 'emc1402'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Datasheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - http://ww1.microchip.com/downloads/en/DeviceDoc/1412.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - https://ww1.microchip.com/downloads/en/DeviceDoc/1402.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * SMSC / Microchip EMC1403, EMC1404, EMC1413, EMC1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Addresses scanned: I2C 0x18, 0x29, 0x4c, 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Prefix: 'emc1403', 'emc1404'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Datasheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - http://ww1.microchip.com/downloads/en/DeviceDoc/1403_1404.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - http://ww1.microchip.com/downloads/en/DeviceDoc/1413_1414.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SMSC / Microchip EMC1422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Addresses scanned: I2C 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Prefix: 'emc1422'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - https://ww1.microchip.com/downloads/en/DeviceDoc/1422.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * SMSC / Microchip EMC1423, EMC1424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Addresses scanned: I2C 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Prefix: 'emc1423', 'emc1424'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - https://ww1.microchip.com/downloads/en/DeviceDoc/1423_1424.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Kalhan Trisal <kalhan.trisal@intel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) The Standard Microsystems Corporation (SMSC) / Microchip EMC14xx chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) contain up to four temperature sensors. EMC14x2 support two sensors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (one internal, one external). EMC14x3 support three sensors (one internal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) two external), and EMC14x4 support four sensors (one internal, three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) external).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) The chips implement three limits for each sensor: low (tempX_min), high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (tempX_max) and critical (tempX_crit.) The chips also implement an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) hysteresis mechanism which applies to all limits. The relative difference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) is stored in a single register on the chip, which means that the relative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) difference between the limit and its hysteresis is always the same for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) all three limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) This implementation detail implies the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * When setting a limit, its hysteresis will automatically follow, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) difference staying unchanged. For example, if the old critical limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) was 80 degrees C, and the hysteresis was 75 degrees C, and you change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) the critical limit to 90 degrees C, then the hysteresis will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) automatically change to 85 degrees C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The hysteresis values can't be set independently. We decided to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) only temp1_crit_hyst writable, while all other hysteresis attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) are read-only. Setting temp1_crit_hyst writes the difference between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) temp1_crit_hyst and temp1_crit into the chip, and the same relative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) hysteresis applies automatically to all other limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * The limits should be set before the hysteresis.