^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ===============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) drm/tegra NVIDIA Tegra GPU and display driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ===============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) NVIDIA Tegra SoCs support a set of display, graphics and video functions via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) the host1x controller. host1x supplies command streams, gathered from a push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) buffer provided directly by the CPU, to its clients via channels. Software,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) or blocks amongst themselves, can use syncpoints for synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Up until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) with Tegra124 the GPU is based on the NVIDIA desktop GPU architecture and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) supported by the drm/nouveau driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) has three parts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - A host1x driver that provides infrastructure and access to the host1x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) services.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - A KMS driver that supports the display controllers as well as a number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) outputs, such as RGB, HDMI, DSI, and DisplayPort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - A set of custom userspace IOCTLs that can be used to submit jobs to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) GPU and video engines via host1x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Driver Infrastructure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) The various host1x clients need to be bound together into a logical device in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) order to expose their functionality to users. The infrastructure that supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) this is implemented in the host1x driver. When a driver is registered with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) infrastructure it provides a list of compatible strings specifying the devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) that it needs. The infrastructure creates a logical device and scan the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) tree for matching device nodes, adding the required clients to a list. Drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) for individual clients register with the infrastructure as well and are added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) to the logical host1x device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Once all clients are available, the infrastructure will initialize the logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) device using a driver-provided function which will set up the bits specific to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) the subsystem and in turn initialize each of its clients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Similarly, when one of the clients is unregistered, the infrastructure will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) destroy the logical device by calling back into the driver, which ensures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) the subsystem specific bits are torn down and the clients destroyed in turn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Host1x Infrastructure Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) -------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .. kernel-doc:: include/linux/host1x.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .. kernel-doc:: drivers/gpu/host1x/bus.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) :export:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Host1x Syncpoint Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .. kernel-doc:: drivers/gpu/host1x/syncpt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) :export:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) KMS driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ==========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) The display hardware has remained mostly backwards compatible over the various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Tegra SoC generations, up until Tegra186 which introduces several changes that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) make it difficult to support with a parameterized driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Display Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Tegra SoCs have two display controllers, each of which can be associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) zero or more outputs. Outputs can also share a single display controller, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) only if they run with compatible display timings. Two display controllers can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) also share a single framebuffer, allowing cloned configurations even if modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) on two outputs don't match. A display controller is modelled as a CRTC in KMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) On Tegra186, the number of display controllers has been increased to three. A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) display controller can no longer drive all of the outputs. While two of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) controllers can drive both DSI outputs and both SOR outputs, the third cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) drive any DSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) A display controller controls a set of windows that can be used to composite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) multiple buffers onto the screen. While it is possible to assign arbitrary Z
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ordering to individual windows (by programming the corresponding blending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) registers), this is currently not supported by the driver. Instead, it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) assume a fixed Z ordering of the windows (window A is the root window, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) is, the lowest, while windows B and C are overlaid on top of window A). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) overlay windows support multiple pixel formats and can automatically convert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) from YUV to RGB at scanout time. This makes them useful for displaying video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) content. In KMS, each window is modelled as a plane. Each display controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) has a hardware cursor that is exposed as a cursor plane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) -------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) The type and number of supported outputs varies between Tegra SoC generations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) All generations support at least HDMI. While earlier generations supported the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) very simple RGB interfaces (one per display controller), recent generations no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) longer do and instead provide standard interfaces such as DSI and eDP/DP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Outputs are modelled as a composite encoder/connector pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RGB/LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) This interface is no longer available since Tegra124. It has been replaced by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) the more standard DSI and eDP interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) HDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) by the versatile SOR output, which supports eDP, DP and HDMI. The SOR is able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) to support HDMI 2.0, though support for this is currently not merged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) Although Tegra has supported DSI since Tegra30, the controller has changed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) several ways in Tegra114. Since none of the publicly available development
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) boards prior to Dalmore (Tegra114) have made use of DSI, only Tegra114 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) later are supported by the drm/tegra driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) eDP/DP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) eDP was first introduced in Tegra124 where it was used to drive the display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) panel for notebook form factors. Tegra210 added support for full DisplayPort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) support, though this is currently not implemented in the drm/tegra driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) Userspace Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) The userspace interface provided by drm/tegra allows applications to create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GEM buffers, access and control syncpoints as well as submit command streams
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) to host1x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) GEM Buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) The ``DRM_IOCTL_TEGRA_GEM_CREATE`` IOCTL is used to create a GEM buffer object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) with Tegra-specific flags. This is useful for buffers that should be tiled, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) that are to be scanned out upside down (useful for 3D content).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) After a GEM buffer object has been created, its memory can be mapped by an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) application using the mmap offset returned by the ``DRM_IOCTL_TEGRA_GEM_MMAP``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Syncpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) The current value of a syncpoint can be obtained by executing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ``DRM_IOCTL_TEGRA_SYNCPT_READ`` IOCTL. Incrementing the syncpoint is achieved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) using the ``DRM_IOCTL_TEGRA_SYNCPT_INCR`` IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) Userspace can also request blocking on a syncpoint. To do so, it needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) execute the ``DRM_IOCTL_TEGRA_SYNCPT_WAIT`` IOCTL, specifying the value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) the syncpoint to wait for. The kernel will release the application when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) syncpoint reaches that value or after a specified timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) Command Stream Submission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Before an application can submit command streams to host1x it needs to open a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) channel to an engine using the ``DRM_IOCTL_TEGRA_OPEN_CHANNEL`` IOCTL. Client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IDs are used to identify the target of the channel. When a channel is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) longer needed, it can be closed using the ``DRM_IOCTL_TEGRA_CLOSE_CHANNEL``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IOCTL. To retrieve the syncpoint associated with a channel, an application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) can use the ``DRM_IOCTL_TEGRA_GET_SYNCPT``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) After opening a channel, submitting command streams is easy. The application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writes commands into the memory backing a GEM buffer object and passes these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) to the ``DRM_IOCTL_TEGRA_SUBMIT`` IOCTL along with various other parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) such as the syncpoints or relocations used in the job submission.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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