^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Driver for PXA25x LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) The driver supports the following options, either via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) options=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) For example::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) modprobe pxafb options=vmem:2M,mode:640x480-8,passive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) or on the kernel command line::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) video=pxafb:vmem:2M,mode:640x480-8,passive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) vmem: VIDEO_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Amount of video memory to allocate (can be suffixed with K or M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) for kilobytes or megabytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) mode:XRESxYRES[-BPP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) XRES == LCCR1_PPL + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) YRES == LLCR2_LPP + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The resolution of the display in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pixclock:PIXCLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Pixel clock in picoseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) left:LEFT == LCCR1_BLW + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) right:RIGHT == LCCR1_ELW + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) hsynclen:HSYNC == LCCR1_HSW + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) upper:UPPER == LCCR2_BFW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) lower:LOWER == LCCR2_EFR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) vsynclen:VSYNC == LCCR2_VSW + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Display margins and sync times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) color | mono => LCCR0_CMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) umm...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) active | passive => LCCR0_PAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Active (TFT) or Passive (STN) display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) single | dual => LCCR0_SDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) Single or dual panel passive display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 4pix | 8pix => LCCR0_DPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 4 or 8 pixel monochrome single panel data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) hsync:HSYNC, vsync:VSYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Horizontal and vertical sync. 0 => active low, 1 => active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dpc:DPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Double pixel clock. 1=>true, 0=>false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) outputen:POLARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Output Enable Polarity. 0 => active low, 1 => active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pixclockpol:POLARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pixel clock polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0 => falling edge, 1 => rising edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) Overlay Support for PXA27x and later LCD controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ====================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PXA27x and later processors support overlay1 and overlay2 on-top of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) base framebuffer (although under-neath the base is also possible). They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) support palette and no-palette RGB formats, as well as YUV formats (only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) available on overlay2). These overlays have dedicated DMA channels and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) behave in a similar way as a framebuffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) However, there are some differences between these overlay framebuffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) and normal framebuffers, as listed below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 1. overlay can start at a 32-bit word aligned position within the base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) framebuffer, which means they have a start (x, y). This information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) is encoded into var->nonstd (no, var->xoffset and var->yoffset are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) not for such purpose).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 2. overlay framebuffer is allocated dynamically according to specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 'struct fb_var_screeninfo', the amount is decided by::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) var->xres_virtual * var->yres_virtual * bpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bpp = 16 -- for RGB565 or RGBT555
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bpp = 24 -- for YUV444 packed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bpp = 24 -- for YUV444 planar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bpp = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bpp = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) a. overlay does not support panning in x-direction, thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) var->xres_virtual will always be equal to var->xres
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) b. line length of overlay(s) must be on a 32-bit word boundary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for YUV planar modes, it is a requirement for the component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) with minimum bits per pixel, e.g. for YUV420, Cr component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for one pixel is actually 2-bits, it means the line length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) should be a multiple of 16-pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) c. starting horizontal position (XPOS) should start on a 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) word boundary, otherwise the fb_check_var() will just fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) d. the rectangle of the overlay should be within the base plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) otherwise fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Applications should follow the sequence below to operate an overlay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) framebuffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) a. open("/dev/fb[1-2]", ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) b. ioctl(fd, FBIOGET_VSCREENINFO, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) c. modify 'var' with desired parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1) var->xres and var->yres
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 2) larger var->yres_virtual if more memory is required,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) usually for double-buffering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 3) var->nonstd for starting (x, y) and color format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 4) var->{red, green, blue, transp} if RGB mode is to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) d. ioctl(fd, FBIOPUT_VSCREENINFO, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) e. ioctl(fd, FBIOGET_FSCREENINFO, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) f. mmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) g. ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 3. for YUV planar formats, these are actually not supported within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) framebuffer framework, application has to take care of the offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) and lengths of each component within the framebuffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 4. var->nonstd is used to pass starting (x, y) position and color format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) the detailed bit fields are shown below::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 31 23 20 10 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) +-----------------+---+----------+----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) | ... unused ... |FOR| XPOS | YPOS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) +-----------------+---+----------+----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FOR - color format, as defined by OVERLAY_FORMAT_* in pxafb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - 0 - RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - 1 - YUV444 PACKED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) - 2 - YUV444 PLANAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) - 3 - YUV422 PLANAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) - 4 - YUR420 PLANAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) XPOS - starting horizontal position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) YPOS - starting vertical position
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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