^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Audio Stream in SoundWire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) An audio stream is a logical or virtual connection created between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) (1) System memory buffer(s) and Codec(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) (2) DSP memory buffer(s) and Codec(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) (3) FIFO(s) and Codec(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) (4) Codec(s) and Codec(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) which is typically driven by a DMA(s) channel through the data link. An
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) audio stream contains one or more channels of data. All channels within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) stream must have same sample rate and same sample size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Assume a stream with two channels (Left & Right) is opened using SoundWire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) interface. Below are some ways a stream can be represented in SoundWire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Stream Sample in memory (System memory, DSP memory or FIFOs) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) | L | R | L | R | L | R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example 1: Stereo Stream with L and R channels is rendered from Master to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Slave. Both Master and Slave is using single port. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) | | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) | L + R +----------------------------------+ L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Example 2: Stereo Stream with L and R channels is captured from Slave to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Master. Both Master and Slave is using single port. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) | | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) | L + R +----------------------------------+ L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) +---------------+ <-----------------------+ +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Example 3: Stereo Stream with L and R channels is rendered by Master. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) of the L and R channel is received by two different Slaves. Master and both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Slaves are using single port. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) | Master +---------+------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) | Interface | | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) | | | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) | | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) | L + R +---+------------------------------+ L |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) | (Data) | | | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) +---------------+ | | +-------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) | | +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) | +----------------------> | Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) | | 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) +----------------------------> | R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Example 4: Stereo Stream with L and R channels is rendered by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Master. Both of the L and R channels are received by two different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Slaves. Master and both Slaves are using single port handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) L+R. Each Slave device processes the L + R data locally, typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) based on static configuration or dynamic orientation, and may drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) one or more speakers. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) | Master +---------+------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) | Interface | | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) | | | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) | | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) | L + R +---+------------------------------+ L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) | (Data) | | | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) +---------------+ | | +-------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) | | +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) | +----------------------> | Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) | | 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) +----------------------------> | L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Example 5: Stereo Stream with L and R channel is rendered by two different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Ports of the Master and is received by only single Port of the Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) interface. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) +--------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | +--------------+ +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | | || | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) | | Data Port || L Channel | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) | | 1 |------------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) | | L Channel || | +-----+----+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) | | (Data) || | L + R Channel || Data | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) | Master +----------+ | +---+---------> || Port | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) | Interface | | || 1 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) | +--------------+ | || | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) | | || | +----------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) | | Data Port |------------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) | | 2 || R Channel | Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) | | R Channel || | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | | (Data) || | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) | +--------------+ Clock Signal | L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | +---------------------------> | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) +--------------------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Example 6: Stereo Stream with L and R channel is rendered by 2 Masters, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rendering one channel, and is received by two different Slaves, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) receiving one channel. Both Masters and both Slaves are using single port. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | 1 | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) | L +----------------------------------+ L |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) | 2 | | 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) | R +----------------------------------+ R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) Example 7: Stereo Stream with L and R channel is rendered by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) Masters, each rendering both channels. Each Slave receives L + R. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) is the same application as Example 4 but with Slaves placed on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) separate links. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) | 1 | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) | L + R +----------------------------------+ L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) | 2 | | 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | L + R +----------------------------------+ L + R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Example 8: 4-channel Stream is rendered by 2 Masters, each rendering a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 2 channels. Each Slave receives 2 channels. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) | 1 | | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) | L1 + R1 +----------------------------------+ L1 + R1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) +---------------+ Clock Signal +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) | Master +----------------------------------+ Slave |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) | Interface | | Interface |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) | 2 | | 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) | | Data Signal | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) | L2 + R2 +----------------------------------+ L2 + R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) | (Data) | Data Direction | (Data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) +---------------+ +-----------------------> +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Note1: In multi-link cases like above, to lock, one would acquire a global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) lock and then go on locking bus instances. But, in this case the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) framework(ASoC DPCM) guarantees that stream operations on a card are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) always serialized. So, there is no race condition and hence no need for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) global lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) Note2: A Slave device may be configured to receive all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) transmitted on a link for a given Stream (Example 4) or just a subset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) of the data (Example 3). The configuration of the Slave device is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) handled by a SoundWire subsystem API, but instead by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) snd_soc_dai_set_tdm_slot() API. The platform or machine driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) typically configure which of the slots are used. For Example 4, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) same slots would be used by all Devices, while for Example 3 the Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) Device1 would use e.g. Slot 0 and Slave device2 slot 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) Note3: Multiple Sink ports can extract the same information for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) same bitSlots in the SoundWire frame, however multiple Source ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) shall be configured with different bitSlot configurations. This is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) same limitation as with I2S/PCM TDM usages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SoundWire Stream Management flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) Stream definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (1) Current stream: This is classified as the stream on which operation has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) to be performed like prepare, enable, disable, de-prepare etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (2) Active stream: This is classified as the stream which is already active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) on Bus other than current stream. There can be multiple active streams
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) on the Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SoundWire Bus manages stream operations for each stream getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) rendered/captured on the SoundWire Bus. This section explains Bus operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) done for each of the stream allocated/released on Bus. Following are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) stream states maintained by the Bus for each of the audio stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SoundWire stream states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) Below shows the SoundWire stream states and state transition diagram. ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) +-----------+ +------------+ +----------+ +----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) | ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) | STATE | | STATE | | STATE | | STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) +-----------+ +------------+ +---+--+---+ +----+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ^ ^ ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __| |___________ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) v | v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) +----------+ +-----+------+ +-+--+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) | STATE | | STATE | | STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) +----------+ +------------+ +----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) NOTE: State transitions between ``SDW_STREAM_ENABLED`` and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ``SDW_STREAM_DISABLED`` are only relevant when then INFO_PAUSE flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) supported at the ALSA/ASoC level. Likewise the transition between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STATE`` depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) INFO_RESUME flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) NOTE2: The framework implements basic state transition checks, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) does not e.g. check if a transition from DISABLED to ENABLED is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) on a specific platform. Such tests need to be added at the ALSA/ASoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) Stream State Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) Below section explains the operations done by the Bus on Master(s) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) Slave(s) as part of stream state transitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SDW_STREAM_ALLOCATED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) Allocation state for stream. This is the entry state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) of the stream. Operations performed before entering in this state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (1) A stream runtime is allocated for the stream. This stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) runtime is used as a reference for all the operations performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) on the stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (2) The resources required for holding stream runtime information are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) allocated and initialized. This holds all stream related information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) such as stream type (PCM/PDM) and parameters, Master and Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) interface associated with the stream, stream state etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ``SDW_STREAM_ALLOCATED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) Bus implements below API for allocate a stream which needs to be called once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) per stream. From ASoC DPCM framework, this stream state maybe linked to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .startup() operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int sdw_alloc_stream(char * stream_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) The SoundWire core provides a sdw_startup_stream() helper function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) typically called during a dailink .startup() callback, which performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) stream allocation and sets the stream pointer for all DAIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) connected to a stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SDW_STREAM_CONFIGURED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) Configuration state of stream. Operations performed before entering in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) this state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (1) The resources allocated for stream information in SDW_STREAM_ALLOCATED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) state are updated here. This includes stream parameters, Master(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) and Slave(s) runtime information associated with current stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (2) All the Master(s) and Slave(s) associated with current stream provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) the port information to Bus which includes port numbers allocated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) Master(s) and Slave(s) for current stream and their channel mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ``SDW_STREAM_CONFIGURED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) Bus implements below APIs for CONFIG state which needs to be called by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) the respective Master(s) and Slave(s) associated with stream. These APIs can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) framework, this stream state is linked to .hw_params() operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int sdw_stream_add_master(struct sdw_bus * bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct sdw_stream_config * stream_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct sdw_ports_config * ports_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int sdw_stream_add_slave(struct sdw_slave * slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct sdw_stream_config * stream_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct sdw_ports_config * ports_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SDW_STREAM_PREPARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) Prepare state of stream. Operations performed before entering in this state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (0) Steps 1 and 2 are omitted in the case of a resume operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) where the bus bandwidth is known.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (1) Bus parameters such as bandwidth, frame shape, clock frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) are computed based on current stream as well as already active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) stream(s) on Bus. Re-computation is required to accommodate current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) stream on the Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (2) Transport and port parameters of all Master(s) and Slave(s) port(s) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) computed for the current as well as already active stream based on frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) shape and clock frequency computed in step 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) (3) Computed Bus and transport parameters are programmed in Master(s) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) Slave(s) registers. The banked registers programming is done on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) alternate bank (bank currently unused). Port(s) are enabled for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) already active stream(s) on the alternate bank (bank currently unused).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) This is done in order to not disrupt already active stream(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (4) Once all the values are programmed, Bus initiates switch to alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bank where all new values programmed gets into effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (5) Ports of Master(s) and Slave(s) for current stream are prepared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) programming PrepareCtrl register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ``SDW_STREAM_PREPARED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) Bus implements below API for PREPARE state which needs to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) once per stream. From ASoC DPCM framework, this stream state is linked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) to .prepare() operation. Since the .trigger() operations may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) follow the .prepare(), a direct transition from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREPARED`` is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int sdw_prepare_stream(struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SDW_STREAM_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) Enable state of stream. The data port(s) are enabled upon entering this state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) Operations performed before entering in this state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (1) All the values computed in SDW_STREAM_PREPARED state are programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) in alternate bank (bank currently unused). It includes programming of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) already active stream(s) as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (2) All the Master(s) and Slave(s) port(s) for the current stream are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enabled on alternate bank (bank currently unused) by programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ChannelEn register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (3) Once all the values are programmed, Bus initiates switch to alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bank where all new values programmed gets into effect and port(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) associated with current stream are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ``SDW_STREAM_ENABLED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) Bus implements below API for ENABLE state which needs to be called once per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) stream. From ASoC DPCM framework, this stream state is linked to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .trigger() start operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int sdw_enable_stream(struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SDW_STREAM_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) Disable state of stream. The data port(s) are disabled upon exiting this state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) Operations performed before entering in this state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (1) All the Master(s) and Slave(s) port(s) for the current stream are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) disabled on alternate bank (bank currently unused) by programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ChannelEn register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (2) All the current configuration of Bus and active stream(s) are programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) into alternate bank (bank currently unused).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) (3) Once all the values are programmed, Bus initiates switch to alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) bank where all new values programmed gets into effect and port(s) associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) with current stream are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ``SDW_STREAM_DISABLED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) Bus implements below API for DISABLED state which needs to be called once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) per stream. From ASoC DPCM framework, this stream state is linked to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .trigger() stop operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) When the INFO_PAUSE flag is supported, a direct transition to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ``SDW_STREAM_ENABLED`` is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) For resume operations where ASoC will use the .prepare() callback, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) stream can transition from ``SDW_STREAM_DISABLED`` to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ``SDW_STREAM_PREPARED``, with all required settings restored but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) without updating the bandwidth and bit allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int sdw_disable_stream(struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SDW_STREAM_DEPREPARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) De-prepare state of stream. Operations performed before entering in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) (1) All the port(s) of Master(s) and Slave(s) for current stream are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) de-prepared by programming PrepareCtrl register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (2) The payload bandwidth of current stream is reduced from the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bandwidth requirement of bus and new parameters calculated and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) applied by performing bank switch etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ``SDW_STREAM_DEPREPARED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) Bus implements below API for DEPREPARED state which needs to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) once per stream. ALSA/ASoC do not have a concept of 'deprepare', and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) the mapping from this stream state to ALSA/ASoC operation may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) implementation specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) When the INFO_PAUSE flag is supported, the stream state is linked to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) the .hw_free() operation - the stream is not deprepared on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) TRIGGER_STOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) Other implementations may transition to the ``SDW_STREAM_DEPREPARED``
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) state on TRIGGER_STOP, should they require a transition through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ``SDW_STREAM_PREPARED`` state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int sdw_deprepare_stream(struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SDW_STREAM_RELEASED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) Release state of stream. Operations performed before entering in this state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (1) Release port resources for all Master(s) and Slave(s) port(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) associated with current stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (2) Release Master(s) and Slave(s) runtime resources associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) current stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (3) Release stream runtime resources associated with current stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) After all above operations are successful, stream state is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ``SDW_STREAM_RELEASED``.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) Bus implements below APIs for RELEASE state which needs to be called by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) all the Master(s) and Slave(s) associated with stream. From ASoC DPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) framework, this stream state is linked to .hw_free() operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int sdw_stream_remove_master(struct sdw_bus * bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int sdw_stream_remove_slave(struct sdw_slave * slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) The .shutdown() ASoC DPCM operation calls below Bus API to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) stream assigned as part of ALLOCATED state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) In .shutdown() the data structure maintaining stream state are freed up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .. code-block:: c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void sdw_release_stream(struct sdw_stream_runtime * stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) The SoundWire core provides a sdw_shutdown_stream() helper function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) typically called during a dailink .shutdown() callback, which clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) the stream pointer for all DAIS connected to a stream and releases the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) memory allocated for the stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) Not Supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 1. A single port with multiple channels supported cannot be used between two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) streams or across stream. For example a port with 4 channels cannot be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) to handle 2 independent stereo streams even though it's possible in theory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) in SoundWire.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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