^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) MTD NAND Driver Programming Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) :Author: Thomas Gleixner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The generic NAND driver supports almost all NAND and AG-AND based chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) and connects them to the Memory Technology Devices (MTD) subsystem of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) the Linux Kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This documentation is provided for developers who want to implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) board drivers or filesystem drivers suitable for NAND devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Known Bugs And Assumptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ==========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Documentation hints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) The function and structure docs are autogenerated. Each function and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct member has a short description which is marked with an [XXX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) identifier. The following chapters explain the meaning of those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Function identifiers [XXX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The functions are marked with [XXX] identifiers in the short comment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The identifiers explain the usage and scope of the functions. Following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) identifiers are used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - [MTD Interface]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) These functions provide the interface to the MTD kernel API. They are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) not replaceable and provide functionality which is complete hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) independent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - [NAND Interface]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) These functions are exported and provide the interface to the NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) kernel API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - [GENERIC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Generic functions are not replaceable and provide functionality which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) is complete hardware independent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - [DEFAULT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Default functions provide hardware related functionality which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) suitable for most of the implementations. These functions can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) replaced by the board driver if necessary. Those functions are called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) via pointers in the NAND chip description structure. The board driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) can set the functions which should be replaced by board dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) functions before calling nand_scan(). If the function pointer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) NULL on entry to nand_scan() then the pointer is set to the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) function which is suitable for the detected chip type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Struct member identifiers [XXX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) -------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) The struct members are marked with [XXX] identifiers in the comment. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) identifiers explain the usage and scope of the members. Following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) identifiers are used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - [INTERN]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) These members are for NAND driver internal use only and must not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) modified. Most of these values are calculated from the chip geometry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) information which is evaluated during nand_scan().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - [REPLACEABLE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Replaceable members hold hardware related functions which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) provided by the board driver. The board driver can set the functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) which should be replaced by board dependent functions before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) nand_scan(). If the function pointer is NULL on entry to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) nand_scan() then the pointer is set to the default function which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) suitable for the detected chip type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - [BOARDSPECIFIC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Board specific members hold hardware related information which must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) be provided by the board driver. The board driver must set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) function pointers and datafields before calling nand_scan().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - [OPTIONAL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) Optional members can hold information relevant for the board driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) The generic NAND driver code does not use this information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Basic board driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) For most boards it will be sufficient to provide just the basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) functions and fill out some really board dependent members in the nand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) chip description structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Basic defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) At least you have to provide a nand_chip structure and a storage for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) the ioremap'ed chip address. You can allocate the nand_chip structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) using kmalloc or you can allocate it statically. The NAND chip structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) embeds an mtd structure which will be registered to the MTD subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) You can extract a pointer to the mtd structure from a nand_chip pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) using the nand_to_mtd() helper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Kmalloc based example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct mtd_info *board_mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __iomem *baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) Static example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct nand_chip board_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void __iomem *baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Partition defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) If you want to divide your device into partitions, then define a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) partitioning scheme suitable to your board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NUM_PARTITIONS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct mtd_partition partition_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .name = "Flash partition 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .size = 8 * 1024 * 1024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .name = "Flash partition 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .offset = MTDPART_OFS_NEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .size = MTDPART_SIZ_FULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Hardware control function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) The hardware control function provides access to the control pins of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) NAND chip(s). The access can be done by GPIO pins or by address lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) If you use address lines, make sure that the timing requirements are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) met.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *GPIO based example*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void board_hwcontrol(struct mtd_info *mtd, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) switch(cmd){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case NAND_CTL_SETCLE: /* Set CLE pin high */ break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case NAND_CTL_CLRCLE: /* Set CLE pin low */ break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case NAND_CTL_SETALE: /* Set ALE pin high */ break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case NAND_CTL_CLRALE: /* Set ALE pin low */ break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case NAND_CTL_SETNCE: /* Set nCE pin low */ break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case NAND_CTL_CLRNCE: /* Set nCE pin high */ break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *Address lines based example.* It's assumed that the nCE pin is driven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) by a chip select decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void board_hwcontrol(struct mtd_info *mtd, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct nand_chip *this = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) switch(cmd){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case NAND_CTL_SETCLE: this->legacy.IO_ADDR_W |= CLE_ADRR_BIT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case NAND_CTL_CLRCLE: this->legacy.IO_ADDR_W &= ~CLE_ADRR_BIT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case NAND_CTL_SETALE: this->legacy.IO_ADDR_W |= ALE_ADRR_BIT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case NAND_CTL_CLRALE: this->legacy.IO_ADDR_W &= ~ALE_ADRR_BIT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) Device ready function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) If the hardware interface has the ready busy pin of the NAND chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) connected to a GPIO or other accessible I/O pin, this function is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) to read back the state of the pin. The function has no arguments and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) should return 0, if the device is busy (R/B pin is low) and 1, if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) device is ready (R/B pin is high). If the hardware interface does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) give access to the ready busy pin, then the function must not be defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) and the function pointer this->legacy.dev_ready is set to NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) Init function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) The init function allocates memory and sets up all the board specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) parameters and function pointers. When everything is set up nand_scan()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) is called. This function tries to detect and identify then chip. If a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) chip is found all the internal data fields are initialized accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) The structure(s) have to be zeroed out first and then filled with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) necessary information about the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __init board_init (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct nand_chip *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Allocate memory for MTD device structure and private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!this) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) printk ("Unable to allocate NAND MTD device structure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) board_mtd = nand_to_mtd(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* map physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) baseaddr = ioremap(CHIP_PHYSICAL_ADDRESS, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!baseaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk("Ioremap to access NAND chip failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto out_mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Set address of NAND IO lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) this->legacy.IO_ADDR_R = baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) this->legacy.IO_ADDR_W = baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Reference hardware control function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) this->hwcontrol = board_hwcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Set command delay time, see datasheet for correct value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) this->legacy.chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Assign the device ready function, if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) this->legacy.dev_ready = board_dev_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) this->eccmode = NAND_ECC_SOFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Scan to find existence of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (nand_scan (this, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto out_ior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) out_ior:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iounmap(baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out_mtd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kfree (this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) module_init(board_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) Exit function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) The exit function is only necessary if the driver is compiled as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) module. It releases all resources which are held by the chip driver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unregisters the partitions in the MTD layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void __exit board_cleanup (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Unregister device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) WARN_ON(mtd_device_unregister(board_mtd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Release resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) nand_cleanup(mtd_to_nand(board_mtd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* unmap physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) iounmap(baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Free the MTD device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) kfree (mtd_to_nand(board_mtd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) module_exit(board_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) Advanced board driver functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ===============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) This chapter describes the advanced functionality of the NAND driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) For a list of functions which can be overridden by the board driver see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) the documentation of the nand_chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) Multiple chip control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) The nand driver can control chip arrays. Therefore the board driver must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) provide an own select_chip function. This function must (de)select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) requested chip. The function pointer in the nand_chip structure must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) set before calling nand_scan(). The maxchip parameter of nand_scan()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) defines the maximum number of chips to scan for. Make sure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) select_chip function can handle the requested number of chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) The nand driver concatenates the chips to one virtual chip and provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) this virtual chip to the MTD layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *Note: The driver can only handle linear chip arrays of equally sized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) chips. There is no support for parallel arrays which extend the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) buswidth.*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *GPIO based example*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void board_select_chip (struct mtd_info *mtd, int chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Deselect all chips, set all nCE pins high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GPIO(BOARD_NAND_NCE) |= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (chip >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GPIO(BOARD_NAND_NCE) &= ~ (1 << chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *Address lines based example.* Its assumed that the nCE pins are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) connected to an address decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void board_select_chip (struct mtd_info *mtd, int chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct nand_chip *this = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Deselect all chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) this->legacy.IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) this->legacy.IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case n:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) Hardware ECC support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) Functions and constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) The nand driver supports three different types of hardware ECC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) - NAND_ECC_HW3_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) Hardware ECC generator providing 3 bytes ECC per 256 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) - NAND_ECC_HW3_512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) Hardware ECC generator providing 3 bytes ECC per 512 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) - NAND_ECC_HW6_512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) Hardware ECC generator providing 6 bytes ECC per 512 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) - NAND_ECC_HW8_512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) Hardware ECC generator providing 8 bytes ECC per 512 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) If your hardware generator has a different functionality add it at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) appropriate place in nand_base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) The board driver must provide following functions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) - enable_hwecc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) This function is called before reading / writing to the chip. Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) or initialize the hardware generator in this function. The function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) is called with an argument which let you distinguish between read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) write operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) - calculate_ecc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) This function is called after read / write from / to the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) Transfer the ECC from the hardware to the buffer. If the option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) NAND_HWECC_SYNDROME is set then the function is only called on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) write. See below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) - correct_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) In case of an ECC error this function is called for error detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) and correction. Return 1 respectively 2 in case the error can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) corrected. If the error is not correctable return -1. If your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hardware generator matches the default algorithm of the nand_ecc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) software generator then use the correction function provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) nand_ecc instead of implementing duplicated code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) Hardware ECC with syndrome calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) Many hardware ECC implementations provide Reed-Solomon codes and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) calculate an error syndrome on read. The syndrome must be converted to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) standard Reed-Solomon syndrome before calling the error correction code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) in the generic Reed-Solomon library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) The ECC bytes must be placed immediately after the data bytes in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) to make the syndrome generator work. This is contrary to the usual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) layout used by software ECC. The separation of data and out of band area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) is not longer possible. The nand driver code handles this layout and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) remaining free bytes in the oob area are managed by the autoplacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) code. Provide a matching oob-layout in this case. See rts_from4.c and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) diskonchip.c for implementation reference. In those cases we must also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) use bad block tables on FLASH, because the ECC layout is interfering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) with the bad block marker positions. See bad block table support for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) Bad block table support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) Most NAND chips mark the bad blocks at a defined position in the spare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) area. Those blocks must not be erased under any circumstances as the bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) block information would be lost. It is possible to check the bad block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mark each time when the blocks are accessed by reading the spare area of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) the first page in the block. This is time consuming so a bad block table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) The nand driver supports various types of bad block tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) - Per device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) The bad block table contains all bad block information of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) which can consist of multiple chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) - Per chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) A bad block table is used per chip and contains the bad block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) information for this particular chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) - Fixed offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) The bad block table is located at a fixed offset in the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) (device). This applies to various DiskOnChip devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) - Automatic placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) The bad block table is automatically placed and detected either at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) the end or at the beginning of a chip (device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) - Mirrored tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) The bad block table is mirrored on the chip (device) to allow updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) of the bad block table without data loss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) nand_scan() calls the function nand_default_bbt().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) nand_default_bbt() selects appropriate default bad block table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) descriptors depending on the chip information which was retrieved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) nand_scan().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) The standard policy is scanning the device for bad blocks and build a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ram based bad block table which allows faster access than always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) checking the bad block information on the flash chip itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) Flash based tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) It may be desired or necessary to keep a bad block table in FLASH. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) AG-AND chips this is mandatory, as they have no factory marked bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) blocks. They have factory marked good blocks. The marker pattern is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) erased when the block is erased to be reused. So in case of powerloss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) before writing the pattern back to the chip this block would be lost and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) added to the bad blocks. Therefore we scan the chip(s) when we detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) them the first time for good blocks and store this information in a bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) block table before erasing any of the blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) The blocks in which the tables are stored are protected against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) accidental access by marking them bad in the memory bad block table. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) bad block table management functions are allowed to circumvent this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) The simplest way to activate the FLASH based bad block table support is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) to set the option NAND_BBT_USE_FLASH in the bbt_option field of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) nand chip structure before calling nand_scan(). For AG-AND chips is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) this done by default. This activates the default FLASH based bad block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) table functionality of the NAND driver. The default bad block table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) options are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) - Store bad block table per chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) - Use 2 bits per block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) - Automatic placement at the end of the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) - Use mirrored tables with version numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) - Reserve 4 blocks at the end of the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) User defined tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) User defined tables are created by filling out a nand_bbt_descr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) structure and storing the pointer in the nand_chip structure member
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bbt_td before calling nand_scan(). If a mirror table is necessary a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) second structure must be created and a pointer to this structure must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) stored in bbt_md inside the nand_chip structure. If the bbt_md member
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) is set to NULL then only the main table is used and no scan for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mirrored table is performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) The most important field in the nand_bbt_descr structure is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) options field. The options define most of the table properties. Use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) predefined constants from rawnand.h to define the options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) - Number of bits per block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) The supported number of bits is 1, 2, 4, 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) - Table per chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) Setting the constant NAND_BBT_PERCHIP selects that a bad block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) table is managed for each chip in a chip array. If this option is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) set then a per device bad block table is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) - Table location is absolute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) Use the option constant NAND_BBT_ABSPAGE and define the absolute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) page number where the bad block table starts in the field pages. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) you have selected bad block tables per chip and you have a multi chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) array then the start page must be given for each chip in the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) array. Note: there is no scan for a table ident pattern performed, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) the fields pattern, veroffs, offs, len can be left uninitialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) - Table location is automatically detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) The table can either be located in the first or the last good blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) of the chip (device). Set NAND_BBT_LASTBLOCK to place the bad block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) table at the end of the chip (device). The bad block tables are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) marked and identified by a pattern which is stored in the spare area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) of the first page in the block which holds the bad block table. Store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) a pointer to the pattern in the pattern field. Further the length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) the pattern has to be stored in len and the offset in the spare area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) must be given in the offs member of the nand_bbt_descr structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) For mirrored bad block tables different patterns are mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) - Table creation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) Set the option NAND_BBT_CREATE to enable the table creation if no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) table can be found during the scan. Usually this is done only once if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) a new chip is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) - Table write support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) Set the option NAND_BBT_WRITE to enable the table write support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) This allows the update of the bad block table(s) in case a block has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) to be marked bad due to wear. The MTD interface function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) block_markbad is calling the update function of the bad block table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) If the write support is enabled then the table is updated on FLASH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) Note: Write support should only be enabled for mirrored tables with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) version control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) - Table version control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) Set the option NAND_BBT_VERSION to enable the table version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) control. It's highly recommended to enable this for mirrored tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) with write support. It makes sure that the risk of losing the bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) block table information is reduced to the loss of the information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) about the one worn out block which should be marked bad. The version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) is stored in 4 consecutive bytes in the spare area of the device. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) position of the version number is defined by the member veroffs in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) the bad block table descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) - Save block contents on write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) In case that the block which holds the bad block table does contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) other useful information, set the option NAND_BBT_SAVECONTENT. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) the bad block table is written then the whole block is read the bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) block table is updated and the block is erased and everything is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) written back. If this option is not set only the bad block table is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) written and everything else in the block is ignored and erased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) - Number of reserved blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) For automatic placement some blocks must be reserved for bad block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) table storage. The number of reserved blocks is defined in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) maxblocks member of the bad block table description structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) Reserving 4 blocks for mirrored tables should be a reasonable number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) This also limits the number of blocks which are scanned for the bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) block table ident pattern.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) Spare area (auto)placement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) The nand driver implements different possibilities for placement of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) filesystem data in the spare area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) - Placement defined by fs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) - Automatic placement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) The default placement function is automatic placement. The nand driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) has built in default placement schemes for the various chiptypes. If due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) to hardware ECC functionality the default placement does not fit then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) the board driver can provide a own placement scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) File system drivers can provide a own placement scheme which is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) instead of the default placement scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) Placement schemes are defined by a nand_oobinfo structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct nand_oobinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int useecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int eccbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int eccpos[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int oobfree[8][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) - useecc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) The useecc member controls the ecc and placement function. The header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) file include/mtd/mtd-abi.h contains constants to select ecc and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) placement. MTD_NANDECC_OFF switches off the ecc complete. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) not recommended and available for testing and diagnosis only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MTD_NANDECC_PLACE selects caller defined placement,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MTD_NANDECC_AUTOPLACE selects automatic placement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) - eccbytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) The eccbytes member defines the number of ecc bytes per page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) - eccpos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) The eccpos array holds the byte offsets in the spare area where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ecc codes are placed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) - oobfree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) The oobfree array defines the areas in the spare area which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) used for automatic placement. The information is given in the format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {offset, size}. offset defines the start of the usable area, size the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) length in bytes. More than one area can be defined. The list is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) terminated by an {0, 0} entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) Placement defined by fs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) The calling function provides a pointer to a nand_oobinfo structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) which defines the ecc placement. For writes the caller must provide a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) spare area buffer along with the data buffer. The spare area buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) is (number of pages) \* (size of spare area). For reads the buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) is (number of pages) \* ((size of spare area) + (number of ecc steps per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) page) \* sizeof (int)). The driver stores the result of the ecc check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) for each tuple in the spare buffer. The storage sequence is::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) <spare data page 0><ecc result 0>...<ecc result n>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) <spare data page n><ecc result 0>...<ecc result n>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) This is a legacy mode used by YAFFS1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) If the spare area buffer is NULL then only the ECC placement is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) according to the given scheme in the nand_oobinfo structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) Automatic placement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) Automatic placement uses the built in defaults to place the ecc bytes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) the spare area. If filesystem data have to be stored / read into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) spare area then the calling function must provide a buffer. The buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) size per page is determined by the oobfree array in the nand_oobinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) If the spare area buffer is NULL then only the ECC placement is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) according to the default builtin scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) Spare area autoplacement default schemes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ----------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 256 byte pagesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ======== ================== ===================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) Offset Content Comment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ======== ================== ===================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 0x00 ECC byte 0 Error correction code byte 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 0x01 ECC byte 1 Error correction code byte 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 0x02 ECC byte 2 Error correction code byte 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0x03 Autoplace 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0x04 Autoplace 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 0x05 Bad block marker If any bit in this byte is zero, then this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) block is bad. This applies only to the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) page in a block. In the remaining pages this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) byte is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0x06 Autoplace 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 0x07 Autoplace 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ======== ================== ===================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 512 byte pagesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ============= ================== ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) Offset Content Comment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ============= ================== ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 0x00 ECC byte 0 Error correction code byte 0 of the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 256 Byte data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 0x01 ECC byte 1 Error correction code byte 1 of the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 0x02 ECC byte 2 Error correction code byte 2 of the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 0x03 ECC byte 3 Error correction code byte 0 of the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0x04 reserved reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 0x05 Bad block marker If any bit in this byte is zero, then this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) block is bad. This applies only to the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) page in a block. In the remaining pages this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) byte is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 0x06 ECC byte 4 Error correction code byte 1 of the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0x07 ECC byte 5 Error correction code byte 2 of the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 0x08 - 0x0F Autoplace 0 - 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ============= ================== ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 2048 byte pagesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) =========== ================== ================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) Offset Content Comment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) =========== ================== ================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 0x00 Bad block marker If any bit in this byte is zero, then this block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) is bad. This applies only to the first page in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) block. In the remaining pages this byte is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 0x01 Reserved Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 0x02-0x27 Autoplace 0 - 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0x28 ECC byte 0 Error correction code byte 0 of the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 256 Byte data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 0x29 ECC byte 1 Error correction code byte 1 of the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0x2A ECC byte 2 Error correction code byte 2 of the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 256 Bytes data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 0x2B ECC byte 3 Error correction code byte 0 of the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 0x2C ECC byte 4 Error correction code byte 1 of the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 0x2D ECC byte 5 Error correction code byte 2 of the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 0x2E ECC byte 6 Error correction code byte 0 of the third
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 0x2F ECC byte 7 Error correction code byte 1 of the third
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 0x30 ECC byte 8 Error correction code byte 2 of the third
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 0x31 ECC byte 9 Error correction code byte 0 of the fourth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 0x32 ECC byte 10 Error correction code byte 1 of the fourth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 0x33 ECC byte 11 Error correction code byte 2 of the fourth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 0x34 ECC byte 12 Error correction code byte 0 of the fifth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 0x35 ECC byte 13 Error correction code byte 1 of the fifth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 0x36 ECC byte 14 Error correction code byte 2 of the fifth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 0x37 ECC byte 15 Error correction code byte 0 of the sixth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 0x38 ECC byte 16 Error correction code byte 1 of the sixth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 0x39 ECC byte 17 Error correction code byte 2 of the sixth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 0x3A ECC byte 18 Error correction code byte 0 of the seventh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 0x3B ECC byte 19 Error correction code byte 1 of the seventh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 0x3C ECC byte 20 Error correction code byte 2 of the seventh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 0x3D ECC byte 21 Error correction code byte 0 of the eighth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 0x3E ECC byte 22 Error correction code byte 1 of the eighth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 0x3F ECC byte 23 Error correction code byte 2 of the eighth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 256 Bytes of data in this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) =========== ================== ================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) Filesystem support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) The NAND driver provides all necessary functions for a filesystem via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) the MTD interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) Filesystems must be aware of the NAND peculiarities and restrictions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) One major restrictions of NAND Flash is, that you cannot write as often
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) as you want to a page. The consecutive writes to a page, before erasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) it again, are restricted to 1-3 writes, depending on the manufacturers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) specifications. This applies similar to the spare area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) Therefore NAND aware filesystems must either write in page size chunks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) or hold a writebuffer to collect smaller writes until they sum up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pagesize. Available NAND aware filesystems: JFFS2, YAFFS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) The spare area usage to store filesystem data is controlled by the spare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) area placement functionality which is described in one of the earlier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) chapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) Tools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) =====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) The MTD project provides a couple of helpful tools to handle NAND Flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) - flasherase, flasheraseall: Erase and format FLASH partitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) - nandwrite: write filesystem images to NAND FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) - nanddump: dump the contents of a NAND FLASH partitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) These tools are aware of the NAND restrictions. Please use those tools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) instead of complaining about errors which are caused by non NAND aware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) access methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) Constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) =========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) This chapter describes the constants which might be relevant for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) driver developer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) Chip option constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) Constants for chip id table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) These constants are defined in rawnand.h. They are OR-ed together to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) describe the chip functionality::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Buswitdh is 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define NAND_BUSWIDTH_16 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Device supports partial programming without padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define NAND_NO_PADDING 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Chip has cache program function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define NAND_CACHEPRG 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Chip has copy back function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define NAND_COPYBACK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* AND Chip which has 4 banks and a confusing page / block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * assignment. See Renesas datasheet for further information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define NAND_IS_AND 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Chip has a array of 4 pages which can be read without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * additional ready /busy waits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define NAND_4PAGE_ARRAY 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) Constants for runtime options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) These constants are defined in rawnand.h. They are OR-ed together to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) describe the functionality::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* The hw ecc generator provides a syndrome instead a ecc value on read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * This can only work if we have the ecc bytes directly behind the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define NAND_HWECC_SYNDROME 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ECC selection constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) Use these constants to select the ECC algorithm::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* No ECC. Usage is not recommended ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define NAND_ECC_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Software ECC 3 byte ECC per 256 Byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define NAND_ECC_SOFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Hardware ECC 3 byte ECC per 256 Byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define NAND_ECC_HW3_256 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* Hardware ECC 3 byte ECC per 512 Byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define NAND_ECC_HW3_512 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Hardware ECC 6 byte ECC per 512 Byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define NAND_ECC_HW6_512 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Hardware ECC 8 byte ECC per 512 Byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define NAND_ECC_HW8_512 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) Hardware control related constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) These constants describe the requested hardware access function when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) boardspecific hardware control function is called::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Select the chip by setting nCE to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define NAND_CTL_SETNCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Deselect the chip by setting nCE to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define NAND_CTL_CLRNCE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Select the command latch by setting CLE to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define NAND_CTL_SETCLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Deselect the command latch by setting CLE to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define NAND_CTL_CLRCLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Select the address latch by setting ALE to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define NAND_CTL_SETALE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Deselect the address latch by setting ALE to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define NAND_CTL_CLRALE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Set write protection by setting WP to high. Not used! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define NAND_CTL_SETWP 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Clear write protection by setting WP to low. Not used! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define NAND_CTL_CLRWP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) Bad block table related constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ---------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) These constants describe the options used for bad block table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) descriptors::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* Options for the bad block table descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* The number of bits used per block in the bbt on the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define NAND_BBT_NRBITS_MSK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define NAND_BBT_1BIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define NAND_BBT_2BIT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define NAND_BBT_4BIT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define NAND_BBT_8BIT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* The bad block table is in the last good block of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define NAND_BBT_LASTBLOCK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* The bbt is at the given page, else we must scan for the bbt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define NAND_BBT_ABSPAGE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* bbt is stored per chip on multichip devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define NAND_BBT_PERCHIP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* bbt has a version counter at offset veroffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define NAND_BBT_VERSION 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Create a bbt if none axists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define NAND_BBT_CREATE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Write bbt if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define NAND_BBT_WRITE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Read and write back block contents when writing bbt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define NAND_BBT_SAVECONTENT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) Structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ==========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) This chapter contains the autogenerated documentation of the structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) which are used in the NAND driver and might be relevant for a driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) developer. Each struct member has a short description which is marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) with an [XXX] identifier. See the chapter "Documentation hints" for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) explanation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .. kernel-doc:: include/linux/mtd/rawnand.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) :internal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) Public Functions Provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) This chapter contains the autogenerated documentation of the NAND kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) API functions which are exported. Each function has a short description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) which is marked with an [XXX] identifier. See the chapter "Documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) hints" for an explanation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) :export:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .. kernel-doc:: drivers/mtd/nand/raw/nand_ecc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) :export:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) Internal Functions Provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ===========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) This chapter contains the autogenerated documentation of the NAND driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) internal functions. Each function has a short description which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) marked with an [XXX] identifier. See the chapter "Documentation hints"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) for an explanation. The functions marked with [DEFAULT] might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) relevant for a board driver developer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) :internal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .. kernel-doc:: drivers/mtd/nand/raw/nand_bbt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) :internal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) Credits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) =======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) The following people have contributed to the NAND driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) 1. Steven J. Hill\ sjhill@realitydiluted.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) 2. David Woodhouse\ dwmw2@infradead.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) 3. Thomas Gleixner\ tglx@linutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) A lot of users have provided bugfixes, improvements and helping hands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) for testing. Thanks a lot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) The following people have contributed to this document:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) 1. Thomas Gleixner\ tglx@linutronix.de
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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