Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) SPI NOR framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Part I - Why do we need this framework?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) ---------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) controller operates agnostic of the specific device attached. However, some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) controllers (such as Freescale's QuadSPI controller) cannot easily handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) In particular, Freescale's QuadSPI controller must know the NOR commands to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) opcodes, addresses, or data payloads; a SPI controller simply knows to send or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) receive bytes (Tx and Rx). Therefore, we must define a new layering scheme under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) which the controller driver is aware of the opcodes, addressing, and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) details of the SPI NOR protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Part II - How does the framework work?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) This framework just adds a new layer between the MTD and the SPI bus driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) With this new layer, the SPI NOR controller driver does not depend on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) m25p80 code anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Before this framework, the layer is like::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)                    MTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)                   m25p80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	       SPI bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	        SPI NOR chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)    After this framework, the layer is like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)                    MTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)               SPI NOR framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)                   m25p80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	       SPI bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	       SPI NOR chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   With the SPI NOR controller driver (Freescale QuadSPI), it looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)                    MTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)               SPI NOR framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)                 fsl-quadSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)          ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	       SPI NOR chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Part III - How can drivers use the framework?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) The main API is spi_nor_scan(). Before you call the hook, a driver should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) initialize the necessary fields for spi_nor{}. Please see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to spi-fsl-qspi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) when you want to write a new driver for a SPI NOR controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Another API is spi_nor_restore(), this is used to restore the status of SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) flash chip such as addressing mode. Call it whenever detach the driver from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) device or reboot the system.