^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The cx88 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Author: Gerd Hoffmann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Documentation missing at the cx88 datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) -------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) MO_OUTPUT_FORMAT (0x310164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .. code-block:: none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Previous default from DScaler: 0x1c1f0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Digit 8: 31-28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 28: PREVREMOD = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Digit 7: 27-24 (0xc = 12 = b1100 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 27: COMBALT = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 26: PAL_INV_PHASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) (DScaler apparently set this to 1, resulted in sucky picture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Digits 6,5: 23-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 25-16: COMB_RANGE = 0x1f [default] (9 bits -> max 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Digit 4: 15-12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 15: DISIFX = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 14: INVCBF = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 13: DISADAPT = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 12: NARROWADAPT = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Digit 3: 11-8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 11: FORCE2H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 10: FORCEREMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 9: NCHROMAEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 8: NREMODEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Digit 2: 7-4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 7-6: YCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 5-4: CCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Digit 1: 3-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 3: RANGE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 2: HACTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 1: HSFMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x47 is the sync byte for MPEG-2 transport stream packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Datasheet incorrectly states to use 47 decimal. 188 is the length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) All DVB compliant frontends output packets with this start code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Hauppauge WinTV cx88 IR information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) -----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) The controls for the mux are GPIO [0,1] for source, and GPIO 2 for muting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ====== ======== =================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GPIO0 GPIO1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ====== ======== =================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0 0 TV Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 1 0 FM radio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0 1 Line-In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1 1 Mono tuner bypass or CD passthru (tuner specific)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ====== ======== =================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GPIO 16(I believe) is tied to the IR port (if present).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) From the data sheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - Register 24'h20004 PCI Interrupt Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - bit [18] IR_SMP_INT Set when 32 input samples have been collected over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - gpio[16] pin into GP_SAMPLE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) What's missing from the data sheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - Setup 4KHz sampling rate (roughly 2x oversampled; good enough for our RC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) compat remote)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - set register 0x35C050 to 0xa80a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - enable sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - set register 0x35C054 to 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - enable the IRQ bit 18 in the interrupt mask register (and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) provide for a handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GP_SAMPLE register is at 0x35C058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Bits are then right shifted into the GP_SAMPLE register at the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) rate; you get an interrupt when a full DWORD is received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) You need to recover the actual RC5 bits out of the (oversampled) IR sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bits. (Hint: look for the 0/1and 1/0 crossings of the RC5 bi-phase data) An
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) actual raw RC5 code will span 2-3 DWORDS, depending on the actual alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) I'm pretty sure when no IR signal is present the receiver is always in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) marking state(1); but stray light, etc can cause intermittent noise values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) as well. Remember, this is a free running sample of the IR receiver state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) over time, so don't assume any sample starts at any particular place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Additional info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) This data sheet (google search) seems to have a lovely description of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RC5 basics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) http://www.atmel.com/dyn/resources/prod_documents/doc2817.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) This document has more data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) http://www.nenya.be/beor/electronics/rc5.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) This document has a how to decode a bi-phase data stream:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) http://www.ee.washington.edu/circuit_archive/text/ir_decode.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) This document has still more info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) http://www.xs4all.nl/~sbp/knowledge/ir/rc5.htm
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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