Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The FPGA subsystem supports reprogramming FPGAs dynamically under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Linux.  Some of the core intentions of the FPGA subsystems are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) * The FPGA subsystem is vendor agnostic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) * The FPGA subsystem separates upper layers (userspace interfaces and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   enumeration) from lower layers that know how to program a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Code should not be shared between upper and lower layers.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   should go without saying.  If that seems necessary, there's probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   framework functionality that can be added that will benefit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   other users.  Write the linux-fpga mailing list and maintainers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   seek out a solution that expands the framework for broad reuse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Generally, when adding code, think of the future.  Plan for reuse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The framework in the kernel is divided into:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) If you are adding a new FPGA or a new method of programming an FPGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) this is the subsystem for you.  Low level FPGA manager drivers contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) the knowledge of how to program a specific device.  This subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) includes the framework in fpga-mgr.c and the low level drivers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) are registered with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FPGA Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FPGA Bridges prevent spurious signals from going out of an FPGA or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) region of an FPGA during programming.  They are disabled before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) programming begins and re-enabled afterwards.  An FPGA bridge may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) actual hard hardware that gates a bus to a CPU or a soft ("freeze")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bridge in FPGA fabric that surrounds a partial reconfiguration region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) of an FPGA.  This subsystem includes fpga-bridge.c and the low level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) drivers that are registered with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FPGA Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) If you are adding a new interface to the FPGA framework, add it on top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) of an FPGA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) The FPGA Region framework (fpga-region.c) associates managers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bridges as reconfigurable regions.  A region may refer to the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FPGA in full reconfiguration or to a partial reconfiguration region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) The Device Tree FPGA Region support (of-fpga-region.c) handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reprogramming FPGAs when device tree overlays are applied.