^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) d) Xilinx IP cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) of standard device types (network, serial, etc.) and miscellaneous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) devices (gpio, LCD, spi, etc). Also, since these devices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) implemented within the fpga fabric every instance of the device can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) synthesised with different options that change the behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Each IP-core has a set of parameters which the FPGA designer can use to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) control how the core is synthesized. Historically, the EDK tool would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extract the device parameters relevant to device drivers and copy them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) into an 'xparameters.h' in the form of #define symbols. This tells the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) device drivers how the IP cores are configured, but it requires the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) to be recompiled every time the FPGA bitstream is resynthesized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) The new approach is to export the parameters into the device tree and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) generate a new device tree each time the FPGA bitstream changes. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) parameters which used to be exported as #defines will now become
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) properties of the device node. In general, device nodes for IP-cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) will take the following form:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) (name): (generic-name)@(base-address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) compatible = "xlnx,(ip-core-name)-(HW_VER)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [, (list of compatible devices), ...];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) reg = <(baseaddr) (size)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) interrupt-parent = <&interrupt-controller-phandle>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) interrupts = < ... >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) xlnx,(parameter1) = "(string-value)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) xlnx,(parameter2) = <(int-value)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (generic-name): an open firmware-style name that describes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) generic class of device. Preferably, this is one word, such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) as 'serial' or 'ethernet'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (ip-core-name): the name of the ip block (given after the BEGIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) directive in system.mhs). Should be in lowercase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) and all underscores '_' converted to dashes '-'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (name): is derived from the "PARAMETER INSTANCE" value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (parameter#): C_* parameters from system.mhs. The C_ prefix is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dropped from the parameter name, the name is converted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) to lowercase and all underscore '_' characters are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) converted to dashes '-'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (HW_VER): from the HW_VER parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Typically, the compatible list will include the exact IP core version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) followed by an older IP core version which implements the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) interface or any other device with the same interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 'reg' and 'interrupts' are all optional properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) For example, the following block from system.mhs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) BEGIN opb_uartlite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PARAMETER INSTANCE = opb_uartlite_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PARAMETER HW_VER = 1.00.b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PARAMETER C_BAUDRATE = 115200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PARAMETER C_DATA_BITS = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PARAMETER C_ODD_PARITY = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PARAMETER C_USE_PARITY = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PARAMETER C_CLK_FREQ = 50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PARAMETER C_BASEADDR = 0xEC100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PARAMETER C_HIGHADDR = 0xEC10FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BUS_INTERFACE SOPB = opb_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PORT OPB_Clk = CLK_50MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PORT Interrupt = opb_uartlite_0_Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PORT RX = opb_uartlite_0_RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PORT TX = opb_uartlite_0_TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PORT OPB_Rst = sys_bus_reset_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) becomes the following device tree node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) opb_uartlite_0: serial@ec100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) device_type = "serial";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatible = "xlnx,opb-uartlite-1.00.b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = <ec100000 10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) interrupt-parent = <&opb_intc_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) interrupts = <1 0>; // got this from the opb_intc parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) current-speed = <d#115200>; // standard serial device prop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clock-frequency = <d#50000000>; // standard serial device prop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) xlnx,data-bits = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) xlnx,odd-parity = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) xlnx,use-parity = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) That covers the general approach to binding xilinx IP cores into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) device tree. The following are bindings for specific devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) i) Xilinx ML300 Framebuffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) Simple framebuffer device from the ML300 reference design (also on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ML403 reference design as well as others).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - resolution = <xres yres> : pixel resolution of framebuffer. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) implementations use a different resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Default is <d#640 d#480>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Default is <d#1024 d#480>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - rotate-display (empty) : rotate display 180 degrees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ii) Xilinx SystemACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) The Xilinx SystemACE device is used to program FPGAs from an FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bitstream stored on a CF card. It can also be used as a generic CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) interface device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) iii) Xilinx EMAC and Xilinx TEMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) Xilinx Ethernet devices. In addition to general xilinx properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) listed above, nodes for these devices should include a phy-handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) property, and may include other common network device properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) like local-mac-address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iv) Xilinx Uartlite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) Xilinx uartlite devices are simple fixed speed serial ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) - current-speed : Baud rate of uartlite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) v) Xilinx hwicap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Xilinx hwicap devices provide access to the configuration logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) of the FPGA through the Internal Configuration Access Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (ICAP). The ICAP enables partial reconfiguration of the FPGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) readback of the configuration information, and some control over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 'warm boots' of the FPGA fabric.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) - xlnx,family : The family of the FPGA, necessary since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) capabilities of the underlying ICAP hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) differ between different families. May be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 'virtex2p', 'virtex4', or 'virtex5'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) - compatible : should contain "xlnx,xps-hwicap-1.00.a" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "xlnx,opb-hwicap-1.00.b".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) vi) Xilinx Uart 16550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) Xilinx UART 16550 devices are very similar to the NS16550 but with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) different register spacing and an offset from the base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) - clock-frequency : Frequency of the clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) - reg-offset : A value of 3 is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) - reg-shift : A value of 2 is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) vii) Xilinx USB Host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) The Xilinx USB host controller is EHCI compatible but with a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) base address for the EHCI registers, and it is always a big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) USB Host controller. The hardware can be configured as high speed only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) or high speed/full speed hybrid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - xlnx,support-usb-fs: A value 0 means the core is built as high speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) only. A value 1 means the core also supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) full speed devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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