^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Spreadtrum SoCs Watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : Should be "sprd,sp9860-wdt".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg : Specifies base physical address and size of the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - interrupts : Exactly one interrupt specifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - timeout-sec : Contain the default watchdog timeout in seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - clock-names : Contain the input clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - clocks : Phandles to input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) watchdog: watchdog@40310000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "sprd,sp9860-wdt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0 0x40310000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) timeout-sec = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) clock-names = "enable", "rtc_enable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };