^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * SBSA (Server Base System Architecture) Generic Watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The SBSA Generic Watchdog Timer is used to force a reset of the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) after two stages of timeout have elapsed. A detailed definition of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) watchdog timer can be found in the ARM document: ARM-DEN-0029 - Server
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Base System Architecture (SBSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: Should at least contain "arm,sbsa-gwdt".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg: Each entry specifies the base physical address of a register frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) and the length of that frame; currently, two frames must be defined,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) in this order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 1: Watchdog control frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 2: Refresh frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - interrupts: Should contain the Watchdog Signal 0 (WS0) SPI (Shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Peripheral Interrupt) number of SBSA Generic Watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - timeout-sec: Watchdog timeout values (in seconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example for FVP Foundation Model v8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) watchdog@2a440000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) compatible = "arm,sbsa-gwdt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) reg = <0x0 0x2a440000 0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) <0x0 0x2a450000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) interrupts = <0 27 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) timeout-sec = <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };