Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Mediatek SoCs Watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	"mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	"mediatek,mt6589-wdt": for MT6589
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg : Specifies base physical address and size of the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - timeout-sec: contains the watchdog timeout in seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - #reset-cells: Should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) watchdog: watchdog@10007000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	compatible = "mediatek,mt8183-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		     "mediatek,mt6589-wdt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg = <0 0x10007000 0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	timeout-sec = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	#reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };