Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Aspeed Watchdog Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	- "aspeed,ast2400-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	- "aspeed,ast2500-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	- "aspeed,ast2600-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - aspeed,reset-type = "cpu|soc|system|none"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)    Reset behavior - Whenever a timeout occurs the watchdog can be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    to generate one of three different, mutually exclusive, types of resets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    Type "none" can be specified to indicate that no resets are to be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    This is useful in situations where another watchdog engine on chip is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)    to perform the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)    If 'aspeed,reset-type=' is not specified the default is to enable system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)    reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)    Reset types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)         - cpu: Reset CPU on watchdog timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)         - soc: Reset 'System on Chip' on watchdog timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)         - system: Reset system on watchdog timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)         - none: No reset is performed on timeout. Assumes another watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)                 engine is responsible for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  - aspeed,alt-boot:    If property is present then boot from alternate block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  - aspeed,external-signal: If property is present then signal is sent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			external reset counter (only WDT1 and WDT2). If not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			specified no external signal is sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  - aspeed,ext-pulse-duration: External signal pulse duration in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Optional properties for AST2500-compatible watchdogs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  - aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			 drive type to push-pull. The default is open-drain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  - aspeed,ext-active-high: If aspeed,external-signal is present and and the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			   is configured as push-pull, then set the pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			   polarity to active-high. The default is active-low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	wdt1: watchdog@1e785000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		compatible = "aspeed,ast2400-wdt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		reg = <0x1e785000 0x1c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		aspeed,reset-type = "system";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		aspeed,external-signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	};