Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Alphascale asm9260 Watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible : should be "alphascale,asm9260-wdt".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg : Specifies base physical address and size of the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks : the clocks feeding the watchdog timer. See clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clock-names : should be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"mod" - source for tick counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	"ahb" - ahb gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - resets : phandle pointing to the system reset controller with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	line index for the watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reset-names : should be set to "wdt_rst".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - timeout-sec : shall contain the default watchdog timeout in seconds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	if unset, the default timeout is 30 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - alphascale,mode : three modes are supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	"hw" - hw reset (default).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	"sw" - sw reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	"debug" - no action is taken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) watchdog0: watchdog@80048000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	compatible = "alphascale,asm9260-wdt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg = <0x80048000 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	clocks = <&acc CLKID_SYS_WDT>, <&acc CLKID_AHB_WDT>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	clock-names = "mod", "ahb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	interrupts = <55>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	resets = <&rst WDT_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reset-names = "wdt_rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	timeout-sec = <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	alphascale,mode = "hw";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };