^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * OMAP HDQ One wire bus master controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : should be "ti,omap3-1w" or "ti,am4372-hdq"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg : Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - interrupts : interrupt line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - ti,hwmods : "hdq1w"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - ti,mode: should be "hdq": HDQ mode "1w": one-wire mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) If not specified HDQ mode is implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - From omap3.dtsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) hdqw1w: 1w@480b2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) compatible = "ti,omap3-1w";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) reg = <0x480b2000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) interrupts = <58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ti,hwmods = "hdq1w";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ti,mode = "hdq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };