^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * OHCI controller, NXP ohci-nxp variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: must be "nxp,ohci-nxp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: The OHCI interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - transceiver: phandle of the associated ISP1301 device - this is necessary for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) the UDC controller for connecting to the USB physical layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example (LPC32xx):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) isp1301: usb-transceiver@2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) compatible = "nxp,isp1301";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) reg = <0x2c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ohci@31020000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "nxp,ohci-nxp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = <0x31020000 0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) interrupt-parent = <&mic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) interrupts = <0x3b 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) transceiver = <&isp1301>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };