^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MSM SoC HSUSB controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) EHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible: Should contain "qcom,ehci-host"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - regs: offset and length of the register set in the memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - usb-phy: phandle for the PHY device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Example EHCI controller device node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ehci: ehci@f9a55000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "qcom,ehci-host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0xf9a55000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) usb-phy = <&usb_otg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) USB PHY with optional OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - compatible: Should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - regs: Offset and length of the register set in the memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - interrupts: interrupt-specifier for the OTG interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - clocks: A list of phandle + clock-specifier pairs for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) clocks listed in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - clock-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "phy" USB PHY reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "core" Protocol engine clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "iface" Interface bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "alt_core" Protocol engine clock for targets with asynchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reset methodology. (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - vdccx-supply: phandle to the regulator for the vdd supply for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) digital circuit operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - v1p8-supply: phandle to the regulator for the 1.8V supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - v3p3-supply: phandle to the regulator for the 3.3V supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - resets: A list of phandle + reset-specifier pairs for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) resets listed in reset-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - reset-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "phy" USB PHY controller reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "link" USB LINK controller reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 1 - PHY control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 2 - PMIC control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) D+/D- USB lines between connectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Mode Eye Diagram test. Start address at which these values will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "do not overwrite default value at this address".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) For example: qcom,phy-init-sequence = < -1 0x63 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - qcom,phy-num: Select number of pyco-phy to use, can be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0 - PHY one, default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1 - Second PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Some platforms may have configuration to allow USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) controller work with any of the two HSPHYs present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - qcom,vdd-levels: This property must be a list of three integer values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (no, min, max) where each value represents either a voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) in microvolts or a value corresponding to voltage corner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) and controller driver therefore enables pull-up explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) before starting controller using usbcmd run/stop bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - extcon: phandles to external connector devices. First phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) should point to external connector, which provide "USB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cable events, the second should point to external connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) device, which provide "USB-HOST" cable events. If one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) the external connector devices is not required empty <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) phandle should be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Example HSUSB OTG controller device node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) usb@f9a55000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) compatible = "qcom,usb-otg-snps";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = <0xf9a55000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) interrupts = <0 134 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dr_mode = "peripheral";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <&gcc GCC_USB_HS_AHB_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clock-names = "phy", "core", "iface";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) vddcx-supply = <&pm8841_s2_corner>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) v1p8-supply = <&pm8941_l6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) v3p3-supply = <&pm8941_l24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reset-names = "phy", "link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) qcom,otg-control = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) qcom,phy-init-sequence = < -1 0x63 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) qcom,vdd-levels = <1 5 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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