^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * NXP LPC32xx SoC USB Device Controller (UDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Must be "nxp,lpc3220-udc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: Physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: The USB interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * USB Device Low Priority Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * USB Device High Priority Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * USB Device DMA Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * External USB Transceiver Interrupt (OTG ATX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - transceiver: phandle of the associated ISP1301 device - this is necessary for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) the UDC controller for connecting to the USB physical layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) isp1301: usb-transceiver@2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "nxp,isp1301";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0x2c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) usbd@31020000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible = "nxp,lpc3220-udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) reg = <0x31020000 0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) interrupt-parent = <&mic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) transceiver = <&isp1301>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };